GMSK Modem Data Pump
Page 20 of 37
MX909A PRELIMINARY INFORMATION
4.4.5 Status Register
This register may be read by the µC to determine the current state of the modem.
Status Register
7 6 5 4 3 2 1 0
DQRDY
Reserved
BFREE
DIBOVF
IRQ
IBEMPTY
CRCFEC
MO/BA
4.4.5.1 Status Register B7: IRQ - Interrupt Request
This bit is set to '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a change
to the Mode Register PSAVE or TX/RX bits.
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by
changing the Mode Register PSAVE or TX/RX bits.
The Status Register DQRDY bit going from '0' to '1' (If DQEN = '1' ).
The Status Register DIBOVF bit going from '0' to '1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the IRQEN bit of the Mode Register is '1', then the chip IRQ output will be pulled low (to V ) whenever the
SS
IRQ bit is '1'.
4.4.5.2 Status Register B6: BFREE - Data Buffer Free
This bit reflects the availability of the Data Buffer and is cleared to '0' whenever a task other than NULL,
RESET or TSO is written to the Command Register.
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when the modem is ready for the µC to write new data to the Data Buffer and the next task to the Command
Register.
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when it has completed a task and any data associated with that task has been placed into the Data Buffer.
The µC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1', but without setting the IRQ bit, by a RESET task or when the Mode Register
PSAVE or TX/RX bits are changed.
4.4.5.3 Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1', also setting the IRQ bit, when less than two bits remain in the
Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a
gap in the transmit output signal.
The bit is also set to '1' by a RESET task or by a change of the Mode Register TX/RX or PSAVE bits, but in
these cases the IRQ bit will not be set.
The bit is cleared to '0' by writing a task other than NULL, RESET or TSO to the Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid-level voltage (V
will be applied to the Tx low pass filter.
)
BIAS
In receive mode this bit will be '0'.
4.4.5.4 Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' (also setting the IRQ bit) when a task is written to the Command
Register too late to allow continuous reception.
The bit is cleared to '0' by reading the Status Register or by writing a RESET task to the Command Register
or by changing the PSAVE or TX/RX bits of the Mode Register.
In transmit mode this bit will be '0'.
¤2001 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
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