VSR CODEC with DRAM CONTROL
9
MX812 PRELIMINARY INFORMATION
ControlTiming Information ......
Timing Specification – Figures 6 and 7
Characteristics
See Note
Min.
Typ.
Max.
Unit
tCSE
tCSH
tHIZ
“CS-Enable to Clock-High”
Last “Clock-High to CS-High”
“CS-High to Reply Output Tri-state”
“CS-High” Time between transactions
“Clock-Cycle” Time
2.0
4.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
2.0
–
tCSOFF
tCK
tNXT
tCH
2.0
2.0
4.0
500
500
250
0
–
“Inter-Byte” Time
–
“Serial Clock-High” Period
“Serial Clock-Low” Period
“Command Data Set-Up” Time
“Command Data Hold” Time
“Reply Data Set-Up” Time
“Repy Data Hold” Time
–
tCL
–
tCDS
tCDH
tRDS
tRDH
–
–
250
50.0
–
–
Address Line Decoding
MA0 to MA21 are the outputs of the internal 22-bit DRAM address counter, which are time multiplexed as ‘Row’
and ‘Column’ addresses onto the DRAM address lines A0 to A10 etc., as shown below.
Memory Size (MS) Bit = “1” – 4Mbit DRAM
Pin
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10/R2
Row Address
MA0
MA2
MA3
MA4
MA5
MA6
MA7
MA8 MA10 MA12 MA14 MA16 MA18 MA20
MA9 MA11 MA13 MA15 MA17 MA19 MA21
Column Address MA1
Memory Size (MS) Bit = “0” – 1Mbit DRAM(s)
Pin
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Row Address
Column Address MA1
MA0
MA2
MA3
MA4
MA5
MA6
MA7
MA8 MA10 MA12 MA14 MA16 MA18
MA9 MA11 MA13 MA15 MA17 MA19
MA20
MA21
RAS1
active
A10/R2
DRAM Selected
“first”
0
1
x
x
active
“second”
x = don't care
Table 4 Address Line Decoding
Sample Rate (SR) Bit
Division
Ratio
Xtal/clock Frequency (MHz)
4.032
4.0
4.096
SR =
SR =
“1”
“0”
64 kbps
128 kbps
62.5 kbps
31.25 kbps
63 kbps
31.5 kbps
64 kbps
32 kbps
Internal Clock Rate
Local Decoder Clock
125 kHz
126 kHz
128 kHz
Table 5 Sampling Clock Rates Available
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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CMLMICRO [ CML MICROCIRCUITS ]
