VSR CODEC with DRAM CONTROL
9
MX812 PRELIMINARY INFORMATION
Control Timing Information ......
Timing Specification –
Figures 6 and 7
Characteristics
t
CSE
t
CSH
t
HIZ
t
CSOFF
t
CK
t
NXT
t
CH
t
CL
t
CDS
t
CDH
t
RDS
t
RDH
“CS-Enable to Clock-High”
Last “Clock-High to CS-High”
“CS-High to Reply Output Tri-state”
“CS-High” Time between transactions
“Clock-Cycle” Time
“Inter-Byte” Time
“Serial Clock-High” Period
“Serial Clock-Low” Period
“Command Data Set-Up” Time
“Command Data Hold” Time
“Reply Data Set-Up” Time
“Repy Data Hold” Time
See Note
Min.
2.0
4.0
–
2.0
2.0
4.0
500
500
250
0
250
50.0
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
–
–
2.0
–
–
–
–
–
–
–
–
–
Unit
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
Address Line Decoding
MA0 to MA21 are the outputs of the internal 22-bit DRAM address counter, which are time multiplexed as ‘Row’
and ‘Column’ addresses onto the DRAM address lines A0 to A10 etc., as shown below.
Memory Size (MS) Bit = “1” – 4Mbit DRAM
Pin
Row Address
Column Address
A0
MA0
MA1
A1
MA2
MA3
A2
MA4
MA5
A3
MA6
MA7
A4
MA8
MA9
A5
MA10
MA11
A6
MA12
MA13
A7
A8
A9
MA18
MA19
A10/R2
MA20
MA21
MA14 MA16
MA15 MA17
Memory Size (MS) Bit = “0” – 1Mbit DRAM(s)
Pin
Row Address
Column Address
A0
MA0
MA1
A1
MA2
MA3
A2
MA4
MA5
A3
MA6
MA7
A4
MA8
MA9
A5
MA10
MA11
A6
MA12
MA13
A7
A8
A9
MA18
MA19
MA14 MA16
MA15 MA17
MA20
0
1
MA21
x
x
x = don't care
RAS1
active
A10/R2
active
DRAM Selected
“first”
“second”
Table 4 Address Line Decoding
Sample Rate (SR) Bit
Division
Ratio
64 kbps
128 kbps
Xtal/clock Frequency (MHz)
4.0
4.032
62.5 kbps
31.25 kbps
125 kHz
63 kbps
31.5 kbps
Internal Clock Rate
126 kHz
4.096
64 kbps
32 kbps
128 kHz
SR =
SR =
“1”
“0”
Local Decoder Clock
Table 5 Sampling Clock Rates Available
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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CMLMICRO [ CML MICROCIRCUITS ]
