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MX812 参数 Datasheet PDF下载

MX812图片预览
型号: MX812
PDF下载: 下载PDF文件 查看货源
内容描述: VSR CODEC与DRAM控制 [VSR CODEC WITH DRAM CONTROL]
分类和应用: 动态存储器
文件页数/大小: 14 页 / 173 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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VSR CODEC with DRAM CONTROL  
13  
MX812 PRELIMINARY INFORMATION  
Package Outline  
Figure 11 shows the MX812J Ceramic Dual In-Line, or Cerdip, Package. The MX812DW is  
shown in Figure 12. Pin 1 is marked with an indent spot on each chip. Pins number counter-  
clockwise when viewed from the top side.  
Handling Precautions  
The MX812 is a CMOS LSI circuit which includes input protection. However, precautions should  
be taken to prevent static discharges which may cause damage.  
ä
ä
A
K
J
ä
B
ä
L
Package Tolerances  
Pin  
1
Dimension  
Min.  
Max.  
in,(mm)  
1.44 (36.58)  
0.51 (13.06)  
0.18 (4.49)  
0.12 (3.0)  
0.10 (2.54)  
0.018 (0.45)  
0.055 (1.39)  
0.02 (.50)  
1.46 (37.05)  
0.53 (13.36)  
0.220 (5.57)  
0.15 (3.81)  
typical  
A
B
C
D
E
F
G
H
J
C
D
H
ä
ä
ä
ä
ä
G
E
F
typical  
typical  
0.05 (1.30)  
0.62 (15.70)  
typical  
0.61 (15.50)  
0.670 (17.0)  
0.009 (0.25)  
K
L
typical  
Figure 11 - MX812J 28-pin Cerdip  
A
C
H
B
D
F
G
E
Pin  
1
Package Tolerances  
Dimension Min.  
in,(mm)  
Max.  
0.698 (17.72)  
0.706 (17.97)  
0.299 (7.59)  
typical  
A
B
C
D
E
F
G
H
J
K
L
L
0.291 (7.39)  
0.092 (2.33)  
0.004 (0.102)  
0.014 (0.36)  
0.050 (1.27)  
0.026 (0.66)  
0.096 (2.43)  
5
0.020 (0.51)  
0.025 (0.63)  
0.041 (1.04)  
0.009 (0.23)  
5
M
K
0.012 (0.304)  
0.018 (0.46)  
typical  
N
J
P
typical  
0.104 (2.64)  
typical  
R
0.040 (1.02)  
typical  
typical  
M
N
P
R
0.011 (0.28)  
typical  
0.39 (9.91)  
0.414 (10.51)  
Figure 12 - MX812DW SOIC-28 Package  
© 1997 MXCOM Inc.  
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054  
Doc. # 20480076.003  
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA  
All trademarks and service marks are held by their respective companies.  
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