VSR CODEC with DRAM CONTROL
5
MX812 PRELIMINARY INFORMATION
Application Information ......
+ 5.0V
+ 5.0V
VCC
VDD
VCC
VCC
VDD
WE
CAS
W
WE
W
W
CAS
RAS
A10
A9
CAS
CAS
RAS
CAS
RAS
RAS1
RAS1
A10/R2
A10/R2
A9
A8
A9
A8
A9
A8
A9
A8
A8
A7
A6
A7
A7
A6
A7
A6
A5
A4
A7
4Mbit.
DRAM
1Mbit.
DRAM.
No.1
1Mbit.
DRAM.
No.2
MX812
A6
A5
A4
MX812
A6
A5
A4
A5
A4
A5
A4
A3
A2
A1
A0
A3
A2
A3
A2
A1
A0
A3
A2
A1
A3
A2
A1
A1
A0
Q
A0
Q
A0
Q
D
DGND
D
D
D
D
DGND
VSS
V
VSS
SS
Figure 4 - Example DRAM Connections
Choice of DRAM Devices
DRAM devices chosen should be standard 1,048,576 x 1 or 4,194,304 x 1 Dynamic Random Access
memories, with ‘CAS before RAS’ refresh, and a Row Address access time of 200 nano-seconds or less.
BANK
A
'HC00
SELECT B
'HC04
INPUTS
WE
CAS
RAS1
A10/R2
A9
W
W
CAS
RAS
A10
A9
CAS
RAS
A10
A9
A8
A8
A8
A7
A7
A7
4Mbit
DRAM
No. 1
4Mbit
DRAM
No. 2
A6
A6
A5
A4
A6
A5
A4
MX812
A5
A4
A3
A2
A1
A0
A3
A2
A1
A3
A2
A1
A0
Q
A0
Q
D
D
D
Figure 5 - Use of External Elements to Drive Two 4-MBit DRAM Chips
Driving Two 4-MBit DRAM Sections
By adding external logic circuitry, the MX812 can be configured
to drive two 4-MBit DRAM sections. This will have the effect of
doubling the available storage time. i.e. 4 minutes at 32kbps.
With reference to the circuitry shown in Figure 5:
With the Mode Register MS Bit set to “0” the MX812 treats the
DRAM sections as two 1-Mbit devices. The external logic makes
each 4-MBit DRAM appear as four 1-MBit banks selected by the
Bank Select lines ‘A’ and ‘B.’
Bank Select
Inputs
DRAM No 1
Pages
0 – 1023
DRAM No 2
Pages
1024 – 2047
A
B
0
1
0
1
0
0
1
1
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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