VSR CODEC with DRAM CONTROL
8
MX812 PRELIMINARY INFORMATION
Control Timing Information
Figure 6 shows the timing parameters for two-way communication between the µController and Cellular peripherals on the
“C-BUS.” Figure 7 shows the timing relationships between the Serial Clock and Data.
tCSOFF
CHIP SELECT
tCSE
tCSH
tNXT
tNXT
SERIAL CLOCK
tCK
COMMAND DATA
7
6
5
4
3
2
1
0
7
6
6
5
4
3
2
1
0
7
7
6
6
5
4
3
2
1
1
0
0
MSB
LSB
FIRST DATA BYTE
LAST DATA BYTE
ADDRESS/COMMAND
BYTE
tHIZ
REPLY DATA
7
5
4
3
2
1
0
5
4
3
2
MSB
LSB
Logic level is not important
FIRST REPLY DATA BYTE
LAST REPLY DATA BYTE
Figure 6 - Control Timing Information
tCK
70% VDD
SERIAL CLOCK
(from C)
tCH
tCL
30% VDD
tCDH
tCDS
COMMAND DATA
(from C)
tRDH
tRDS
REPLY DATA
(to C)
Figure 7 - Control Timing Relationships
I bit (idle)
Device Condition
MT bit Command
Buffer Status
IF bit (Flag)
Interrupt
(IRQ) Output
New 'Store, Play or Wait'
C1
Command from C-BUS
C2
C3
Read Status Register
**
**
**
** The value read from the Status Register at these times will include a valid 'Power' reading if the Codec is set to the Encode mode.
Command Executing
C1
C3
C2
Figure 8 - Typical Command Sequences
© 1997 MX•COM Inc.
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CMLMICRO [ CML MICROCIRCUITS ]
