VSR CODEC with DRAM CONTROL
3
MX812 PRELIMINARY INFORMATION
Pin
Function
11
Audio Out: The analog output to the Audio Processor “Play” input when the VSR Codec is
configured as a Decoder. When configured as an active Decoder but with no Play Page commands
(62H) active, the VSR Codec will play-out an idle pattern of “101010........10s”. When not configured as
a Decoder, or Powersaved (Mode Register), this output will be held at VBIAS via an internal 500kΩ
resistor. The output at this pin is unfiltered; an external speechband filter – such as that included on
the MX816/826/836 Audio Processors – will be required. Since this output is centered around VDD/2 a
coupling capacitor is required.
12
EBIAS: The Encoder d.c. internal balancing circuitry line. This pin should be decoupled to VSS by
capacitor C4 (see Figure 2). Note that in the ‘Encode’ mode (Mode Register DE and PS both “0”) the
Codec drives this pin to approximately VDD/2 through a very high impedance; it can take more than
one second for the EBIAS voltage to stabilize when power is first applied to this device. A faster start-up
can be achieved by setting Bit DE or PS to “1” for 250mS (approx) during power-up. This will cause
the EBIAS pin to be connected to VBIAS through a resistance of approximately 100kΩ.
13
14
Audio In: The analog input to the VSR Codec in the Encode mode. When not configured as an
Encoder, or Powersaved (Mode Register), this input will be held at VBIAS via an internal 500kΩ resistor.
This pin should be coupled via a capacitor, see Figure 2. As this input does not contain an internal
audio filter, the audio to this pin should be limited to a 3400Hz “speechband” by an external audio filter
– such as included in the MX816/826/836 Audio Processors.
VSS: The “analog” ground connection. See DGND description.
15
16
17
18
19
20
21
22
23
24
A0:
A1:
A2:
A3:
DRAM address line outputs from the MX812.
These pins should be connected to the corresponding address
inputs of the associated DRAM.
A4:
A5:
A6:
A7:
A8:
A9:
25
A10/R2: A dual function output pin selected by the memory size (MS) bit (Mode Register),
as detailed in the table below:
MS bit
“0”
“1”
DRAMs
1Mbits'
4Mbit
Connected To
DRAM No 2 RAS
DRAM A10
This Output
RAS2
A10 Signal
26
27
RAS: An output from the VSR Codec which should be connected to the “Row Address Strobe” pin of
the 4Mbit DRAM or the first 1Mbit DRAM, see Figure 4, Example DRAM connections.
DGND: The digital signal ground connection to the VSR Codec. Both DGND and VSS pins should be
connected to the negative side of the d.c. power supply. However, a printed circuit board should be
laid out so that DGND is connected as closely as possible to the DRAM section ground pins.
28
VDD: Positive supply rail. A single, stable +5-volt supply is required. Levels and voltages within the
VSR Codec are dependent upon this supply. This pin should be decoupled to VSS via capacitor C5,
located close to the MX812 pins.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
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