High Speed GMSK Modem 4k to 64kbps
Page 7 of 20
MX589
4
General Description
4.1
Clock Oscillator Divider
The TX and (nominal) RX data rates are determined by division of the frequency present at the Xtalpin, which
may be generated by the on-chip Xtal oscillator or derived from an external source. Any Xtal/Clock frequency
in the range of 1.0MHz to 5.0MHz for VDD = 3.0V, or 1.0MHz to 8.2MHz for VDD = 5.0V may be used,
depending on the desired data rate.
The division ratio is controlled by the logic level inputs on ClkDivA and ClkDivB pins as shown in Table 4,
together with an indication of how various standard data rates may be derived from common µP Xtal
frequencies.
Xtal/Clk Frequency
DivisionRatio (ClkDiv A/B)
DataRate =
Xtal/Clock Frequency (MHz)
8.192
4.9152
4.096
12.288/3
2.4576
12.288/5
2.048
6.144/3
Inputs
Division Ratio
Xtal Frequency
Data Rate
ClkDivA
ClkDivB
Data Rate (bps)
0
0
1
1
0
1
0
1
128
256
512
1024
64000*
32000
16000
8000
38400*
19200
9600
32000
16000
8000
19200
9600
4800
16000
8000
4000
4800
4000
* VDD ≥ 4.5V
Table 4: Clock/Data Rates
Note: The device operation is not guaranteed above 64kbps or below 4kbps at the relevant supply voltage.
SETTINGS: D/RATE 4800 bps -BT 0.5 - Rx and Tx Enabled
4.9152MHz
VDD
XTAL/CLOCK
XTAL
Tx Enable
RxD
RxC
I/O PORT TxD
TxC
Rx DATA
Rx CLOCK
Tx ClOCK
Tx DATA
ClkDIVA
ClkDIVB
BT
MX589
GMSK MODEM
SERIAL
RxHOLD
Rx S/N
PLLacq
RxDCacq
Tx PS
Rx PS
µCONTROLLER
Figure 4: Minimum µController System Connections
4.2
Receive
4.2.1 Rx Signal Path Description
The function of the RX circuitry is to:
1. Set the incoming signal to a usable level.
2. Clean the signal by filtering.
3. Provide DC level thresholds for clock and data extraction.
4. Provide clock timing information for data extraction and external circuits.
5. Provide RX data in a binary form.
6. Assess signal quality and provide Signal-to-Noise information.
2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 204800103.011
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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