High Speed GMSK Modem 4k to 64kbps
Page 4 of 20
MX589
2
Signal List
Pin No.
Signal
Type
Description
TN/DW/P
1
output
input
The output of the on-chip clock oscillator.
XTAL
XTAL/CLOCK
2
The input to the on-chip Xtal oscillator. A Xtal, or externally derived clock
(fXTAL) pulse input should be connected here. If an externally generated clock
is to be used, it should be connected to this pin and the XTAL pin left
unconnected.
Note: Operation of the MX589 without a suitable Xtal or clock input may
cause device damage.
3
4
5
6
7
8
ClkDivA
ClkDivB
input
input
input
input
input
input
Logic level inputs control the internal clock divider and therefore, the transmit
and receive data rate. See Table 4.
Logic level inputs control the internal clock divider and therefore, the transmit
and receive data rate. See Table 4.
A logic 0 applied to this input will freeze the Clock Extraction and Level
Rx HOLD
RxDCacq
Measurement circuits unless they are in ‘Acquire’ mode.
A logic 1 applied to this input will set the RX Level Measurement circuitry to
the Acquire mode.
PLLacq
A logic 1 applied to this input will set the RX Clock Extraction circuitry to the
‘Acquire’ mode. See Table 5.
Rx PSAVE
A logic 1 applied to this input will powersave all receive circuits except for
RXCLK output (which will continue at the set bit-rate) and cause the RX Data
and RX S/N outputs to go to a logic 0.
9
VBIAS
The internal circuitry bias line, held at VDD/2. This pin must be bypassed to
V
SS by a capacitor mounted close to the pin.
10
11
12
13
Rx FB
Rx Signal In
VSS
Output of the RX Input Amplifier.
Input to RX input amplifier.
Negative supply (GND).
input
power
DOC1
Connections to the RX Level Measurement Circuitry. A capacitor should be
connected from each pin to VSS
.
14
15
DOC2
BT
Connections to the RX Level Measurement Circuitry. A capacitor should be
connected from each pin to VSS
.
A logic level to select the modem BT (the ratio of the TX Filter's -3dB
frequency to the Bit-Rate). A logic 1 = BT of 0.5 and a logic 0 = BT of 0.3.
16
17
Tx Out
Tx Enable
output
input
The TX signal output from the MX589 GMSK Modem.
A logic 1 applied to this input, enables the transmit data path, through the TX
Filter to the TX Out pin. A logic 0 will place the TX Out pin to VBIAS via a
high impedance.
18
19
Tx PSAVE
Tx Data
input
input
A logic 1 applied to this input will powersave all transmit circuits except for
the TX Clock.
The logic level input for the data to be transmitted. This data should be
synchronous with TX CLK.
20
21
22
23
Rx Data
Rx CLK
Tx CLK
Rx S/N
output
output
output
output
A logic level output carrying the received data, synchronous with RX CLK.
A logic level clock output at the received data bit-rate.
A logic level clock output at the transmit-data rate.
A logic level output which may be used as an indication of the quality of the
received signal.
24
VDD
power
Positive supply. A single 5.0V power supply is required. Levels and voltages
within this modem are dependent upon this supply. This pin should be
bypassed to VSS by a capacitor mounted close to the pin.
Table 1: Signal List
2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 204800103.011
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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