High Speed GMSK Modem 4k to 64kbps
Page 11 of 20
MX589
4.3
Transmit
4.3.1 TX Signal Path Description
The binary data applied to the TX Data input is retimed within the chip on each rising edge of the TX Clock
and then converted to a 1-volt peak-to-peak binary signal centered at VBIAS (for VDD= 5.0V)
If the TX Enable input is high, then this internal binary signal will be connected to the input of the lowpass TX
Filter, and the output of the filter connected to the TX Out pin.
Tx Enable
1
0
Tx Filter Input
VDD/5VP-P Data
VBIAS
Tx Out Pin
Filtered Data
VBIAS via 500kΩ
A ‘low’ input to the TX Enable will connect the input of the TX Filter to VBIAS, and disconnect the TX Out pin
from the filter, connecting it instead to VBIAS through a high resistance (nominally 500kΩ).
The TX Filter has a lowpass frequency response, which is approximately gaussian in shape, as shown in
Figure 9, to minimize amplitude and phase distortion of the binary signal while providing sufficient attenuation
of the high frequency-components which would otherwise cause interference into adjacent radio channels.
The actual filter bandwidth to be used in any particular application will be determined by the overall system
requirements. The attenuation- vs. -frequency response of the transmit filtering provided by the MX589 has
been designed to meet the specifications for most GMSK modem systems that are -3dB bandwidth
switchable between 0.3 and 0.5 times the data bit-rate (BT).
Note: An external RC network is required between the TX Out pin and the input to the Frequency Modulator
(see Figure 2 and Figure 3). This network, which can form part of any DC level shifting and gain adjustment
circuitry, forms an important part of the transmit signal filtering. The ground connection to capacitor C1
should be positioned to give maximum attenuation of high-frequency noise into the modulator.
The signal at Tx Out is centered around VBIAS, going positive for logic 1 (high) level inputs to the Tx Data input
and negative for logic 0 (low) inputs. When the transmit circuits are put into a ‘powersave mode’ (by a logic 1
to the Tx PS pin) the output voltage of the Tx Filter will be undefined.
When power is subsequently restored to the Tx filter, its output will take several bit-times to settle. The Tx
Enable input can be used to prevent these abnormal voltages from appearing at the Tx Out pin.
1 BIT PERIOD
TX DATA SAMPLED BY
THE MX589 AT THESE
TX CLOCK AND RX CLOCK OUTPUTS
(MARK/SPACE) DUTY CYCLE NOMINALLY 50%.
INSTANCES
TX CLK
1.0 µs Min.
1.0 µs Min.
DON'T CARE
DATA MUST
BE VALID
TX Data
RX Data
RX CLK
1.0 µs Max.
1.0 µs Max.
DATA INVALID
DATA VALID
EXTERNAL CIRCUITS SHOULD
SAMPLE RX DATA AT THIS TIME
Figure 8: Rx and Tx Clock Data Timings
2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 204800103.011
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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