High Speed GMSK Modem 4k to 64kbps
Page 6 of 20
MX589
Recommended External Component Notes:
1. The RC network formed by R1 and C1 is required between the TX Out pin and the input to the modulator.
This network, which can form part of any DC level shifting and gain adjustment circuitry, forms an
important part of the transmit signal filtering. The ground connection to the capacitor C1 should be
positioned to give maximum attenuation of high-frequency noise into the modulator.
The component values should be chosen so that the product of the resistance and the capacitance is:
For a BT of 0.3
For a BT of 0.5
R1C1 = 0.34/bit rate (bps)
R1C1 = 0.22/bit rate (bps)
Data Rates
BT =- 0.3
(bps)
R1
C1
4000
4800
8000
9600
16000
680pF
680pF
470pF
390pF
470pF
180pF
220pF
180pF
100pF
470pF
470pF
220pF
470pF
150pF
120pF
150pF
120pF
68pF
120kΩ
100kΩ
91kΩ
91kΩ
47kΩ
100kΩ
47kΩ
47kΩ
56kΩ
120kΩ
100kΩ
120kΩ
47kΩ
91kΩ
91kΩ
47kΩ
47kΩ
51kΩ
19200
32,000
38,400 *
64,000 *
* VDD ≥ 4.5V
Table 3: Data Rate vs. BT and Selected External Component Values
Note: In all cases, the value of R1 should not be less than 20.0kΩ, and that the calculated value of C1
includes calculated parasitic capacitance.
2. R3, R4 and C6 form the gain components for the RX Input signal. R3 should be chosen as required by
the signal input level.
3. The values chosen for C2 and C3 (including stray capacitance), should be suitable for the applied VDD
and the frequency of X1.
As a guide: C2 = C3 = 33pF at 1.0MHz falling to 18pF at the maximum frequency.
At 3.0V, C2 = C3 = 33pF falling to 18pF at 5.0MHz the equivalent series resistance of X1 should be less
than 2.0KΩ falling to 150Ω at the maximum frequency. Stray capacitance on the Xtal/Clock circuit pins
must be minimized.
4. C7 and C8 should both be .015µF for a data rate of 8kbps, and inversely proportional to the data rate for
other data rates, e.g. .030µF at 4kbps, 1800pF at 64kbps.
5. The MX589 can operate correctly with the Xtal/Clock frequencies between 1.0MHz and 8.2MHz (VDD
=
5.0V) and 1.0MHz to 5.0MHz (VDD = 3.0V) see Table 1 for examples. For best results, a crystal oscillator
design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning
fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance,
consult your crystal manufacturer. Operation of this device without a Xtal or Clock input may cause
device damage.
2001 MX-COM, Inc.
www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054
Doc. # 204800103.011
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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