RF Quadrature Transceiver / RF Quadrature Receiver
CMX991/CMX992
6.8.2 PLL M Divider C-BUS Addresses $D1 and $D0
8-bit read-only
These registers read the respective values in registers $20 and $21 ($D0 reads back $20 and $D1 reads
back $21), see section 6.8.1 for details of bit functions.
NOTE: $21 b6 indicates the lock status. If set to '1' then the PLL is locked.
6.9
PLL N Divider (CMX991/CMX992)
6.9.1 PLL N Divider
C-BUS Addresses $23 and $22
8-bit write-only
These registers set the N divider value for the PLL (Feedback divider – see Figure 17). The PLL dividers
are not updated until both registers ($23 and $22) have been written. The order of writing these registers is
not important.
$23
$22
7
0
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit:
N14 N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
N14 - N0
Phase Locked Loop N divider value.
(NB: when using an external VCO see the note at the end of section 4.5).
$23, b7
Reserved, set to ‘0’.
6.9.2 PLL N Divider
C-BUS Addresses $D3 and $D2
8-bit read-only
These registers read the respective values in registers $22 and $23 ($D2 reads back $22 and $D3 reads
back $23), see section 6.9.1 for details of bit functions.
2012 CML Microsystems Plc
33
D/991_992/18
CMLMICRO [ CML MICROCIRCUITS ]
