RF Quadrature Transceiver / RF Quadrature Receiver
CMX991/CMX992
All bits of this register are cleared to ‘0’ by a General Reset command.
7
6
5
0
4
0
3
0
2
0
1
0
0
0
Bit:
Gain2
Gain1
Tx Gain Register b7 and b6
I/Q Input Gain Control: These bits control the internal gain applied to input I/Q signals before they
are sent to the I/Q modulator.
b7 B6
0
0
1
1
0
1
0
1
I/Q input gain = 0dB
I/Q input gain = -6dB
I/Q input gain = +6dB
reserved, do not use
Tx Gain Register b5 - b0
Reserved set to ‘0’.
6.7.2 Tx Gain Register
8-bit read-only
C-BUS address $E6
This read-only register mirrors the value in register $16, see section 6.7.1 for details of bit functions.
6.8
IF PLL M Divider (CMX991/CMX992)
6.8.1 PLL M Divider C-BUS Addresses $21 and $20
8-bit write-only
These registers set the M divider value for the PLL (Reference divider – see Figure 17). The PLL dividers
are not updated until both registers ($21 and $20) have been written. The order of writing these registers is
not important. Bits also control the enable of the PLL and charge-pump blocks and these control bits are
active as soon as $21 is written.
$21
$20
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Bit:
E
LD_Synth
CP
M12
M11
M10
M9 M8
M7 M6
M5 M4 M3 M2 M1
M0
M12 - M0
Phase Locked Loop M divider value.
CP
$21, b5 = ’1’ enables the Charge Pump, $21 b5 = ’0’ puts the Charge Pump into high impedance
mode.
LD_Synth
Only write ‘0’ to b6 of $21 (when read, this shows the integer N PLL lock status).
E
$21, b7 = ’1’ enables the PLL; b7 = ’0’ disables the PLL – in this mode an external local oscillator
can be supplied to the IC.
2012 CML Microsystems Plc
32
D/991_992/18
CMLMICRO [ CML MICROCIRCUITS ]
