GMSK Packet Data Modem and RF Transceiver
CMX990
Figure 15 Receive Mode Timing Diagram
Task
Typical time
(bit-times)
Time to receive all bits of task
SFH
R3H
RDB
RSB
RSD
SFH
R3H
RDB
RSB
RSD
Any
56
24
240
8
72
14
18
218
6
t3
t6
t7
Maximum time between first bit of task
entering de-interleave circuit and task
being written to modem
64
1
Time from last bit of task entering de-interleave
circuit to BFREE going to a logic ‘1’ (high)
ã 2004 CML Microsystems Plc
29
D/990/1