GMSK Packet Data Modem and RF Transceiver
CMX990
RSB - Read Single Byte
This task causes the modem to read the next 8 bits and translate them directly (without de-
interleaving or FEC) to a single byte which is placed into the Data Buffer (B7 will represent the
earliest bit received). The BFREE and IRQ bits of the Status 1 Register will then be set to ‘1’ to
indicate that the µC may read the data byte from the Data Buffer and write the next task to the
Command Register.
This task is intended for special tests and channel monitoring - perhaps preceded by an SFS
task.
LFSB - Load Frame Sync Bytes
This task takes 2 bytes from the Data Buffer and updates the Frame Sync detect bytes. The
MSB of byte ‘0’ is compared to the first bit of a received Frame Sync pattern and the LSB of byte
‘1’ is compared to the last bit of a received Frame Sync pattern. This task does not enable
Frame Sync detection.
Unlike other Rx tasks, the data buffer must be loaded before the task is issued and the task must
only be issued ‘between’ received messages, i.e. before the first task for receiving a message
and after the last data is read out of the data buffer.
Once the modem has read the Frame Sync bytes from the Data Buffer, the BFREE and IRQ bits
of the Status 1 Register will be set to ‘1’, indicating to the µC that it may write the next task to the
modem.
SFHZ - Search for Frame Head with Zero Errors
This performs the same task as SFH task but allowing no bits to be in error over the 16-bit Frame
Sync pattern.
RSD - Read Short Data Block
This task causes the modem to read the next 72 bits as a Mobitex Short Data Block.
It will de-scramble and de-interleave the bits, FEC correct and CRC check the resulting 4 data
bytes and place them into the Data Buffer, setting the BFREE and IRQ bits of the Status 1
Register to ‘1’ when the task is complete to indicate that the µC may read the data from the Data
Buffer and write the next task to the modem’s Command Register. The CRCFEC bit will be set
according to the outcome of the CRC check.
Note: in receive mode the CRC checksum circuits are initialised on completion of any task other
than NULL.
SFSZ - Search for Frame Sync with Zero Errors
This performs the same task as SFS task but allowing no bits to be in error over the 16-bit Frame
Sync pattern.
T7H - Transmit 7-byte Frame Head
This task takes 6 bytes of data from the Data Buffer, calculates and appends 8 bits of FEC from
bytes ‘4’ and ‘5’ then transmits the result as a complete Mobitex Frame Head.
Bytes ‘0’ and ‘1’ form the bit sync pattern, bytes ‘2’ and ‘3’ form the frame sync pattern and bytes
‘4’ and ‘5’ are the frame head control bytes. Bit 7 of byte ‘0’ of the Data Buffer is sent first, bit 0
of the FEC byte last.
Once the modem has read the data bytes from the Data Buffer, the BFREE and IRQ bits of the
Status 1 Register will be set to ‘1’, indicating to the µC that it may write the next task and its data
to the modem.
ã 2004 CML Microsystems Plc
26
D/990/1
CMLMICRO [ CML MICROCIRCUITS ]
