PMR Signalling Processor
CMX881
0
Block 4 – Gain and Offset Setup:
Bit:
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P4.8
15
1
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
Fine Input Gain
Reserved - set to '0'
Fine Output Gain 1
Fine Output Gain 2
Output 1 Offset Control
Output 2 Offset Control
Ramp Rate Control
Limiter Setting (all 1's = Vbias +/- 0.5 Vdd)
Special Programming Register (Production Test Only)
1.6.20.1 PROGRAMMING REGISTER Block 0 – Modem Configuration:
$C8 (P0.0-3) MSK Frame SYNC / SYNT and SYND
Bit:
15
1
14
1
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
P0.0
0
0
0
0
MSK SYNC / SYNT LSB
MSK SYNC / SYNT MSB
MSK SYND LSB
P0.1
P0.2
P0.3
0
0
0
1
1
1
0
0
0
0
0
0
MSK SYND MSB
Bits 7 to 0 set the three 16-bit Frame Sync patterns used in Rx MSK data. Bit 7 of the MSB is compared
to the earliest received data. Note: SYNT is the bitwise inverse of SYNC. After a power on reset SYNC
is set to $C4D7 (MPT) and SYND is set to $B433 (PAA).
2004 CML Microsystems Plc
43
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
