PMR Signalling Processor
CMX881
0
1.6.20.5 PROGRAMMING REGISTER Block 4 – Gain and Offset Setup
$C8 (P4.0)
FINE INPUT GAIN
Bit:
15
1
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
P4.0
Fine Input Gain (unsigned integer)
Gain = 20 × log([32768-IG]/32768) IG is the unsigned integer value in the ‘Fine Input Gain’ field
Fine input gain adjustment should be kept within the range 0 to -3.5dB.
$C8 (P4.1)
Reserved
Bit:
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
3
2
2
1
1
0
0
P4.1
Reserved - set to '0'
This register is reserved and should be set to '0'.
$C8 (P4.2-3) FINE OUTPUT GAIN 1 and FINE OUTPUT GAIN 2
Bit:
P4.2
P4.3
15
0
14
0
13
12
11
10
9
8
7
6
5
4
Fine Output Gain 1 (unsigned integer)
0
0
Fine Output Gain 2 (unsigned integer)
Gain = 20 × log([32768-OG]/32768) OG is the unsigned integer value in the ‘Fine Output Gain’ field
Fine output gain adjustment should be kept within the range 0dB to -3.5dB.
$C8 (P4.4-5) OUTPUT 1 OFFSET and OUTPUT 2 OFFSET
Bit:
P4.4
P4.5
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2’s complement offset for MOD_1, resolution = V (A)/16384 per LSB
DD
0
0
2’s complement offset for MOD_2, resolution = V (A)/16384 per LSB
DD
Can be used to compensate for inherent offsets in the output path via MOD_1 (Output 1 Offset) and
MOD_2 (Output 2 Offset). It is recommended that the offset correction is kept within the range +/-50mV.
$C8 (P4.6)
RAMP RATE CONTROL
Bit:
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.6
Ramp Rate Up Control (RRU)
Ramp Rate Down control (RRD)
The ramp-up rate and ramp-down rates can be independently programmed. The ramp rates apply to all
the analogue output ports. They only affect those ports being turned on (ramp-up) or turned off (ramp
down). The ramp rates should be programmed before ramping any outputs.
Time to ramp-up to full gain =
(1 + RRU) × 1.333ms
(1 + RRD) × 1.333ms
Time to ramp down to zero gain =
$C8 (P4.7)
TRANSMIT LIMITER CONTROL
Bit:
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
P4.7
Limiter Setting, resolution = V (A)/16384 per LSB
DD
This unsigned number sets the clipping point (maximum deviation from the centre value) for the MOD_1
and MOD_2 pins. The maximum setting ($2000) is +/- V (A)/2 i.e. output limited from 0 to V (A).
DD DD
Any settings above $2000 will limit to the $2000 setting. The limiter is set to maximum following a C-
BUS Reset or a Power Up Reset. The limiter is only applied to voice signals, not internally generated
audio band signals. The levels of internally generated signals must be limited by setting appropriate
transmit levels.
$C8 (P4.8)
Special Programming Register – do not access.
2004 CML Microsystems Plc
46
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
