PMR Signalling Processor
CMX881
1.6.17
$C6 STATUS: 16-bit read-only
15
14
13
12
0
11
10
9
8
Bit:
Selcall
state
CTCSS
state
DCS
state
Aux ADC
Aux ADC
IRQ
0
Monitor High
Monitor Low
change
change
change
7
6
5
0
4
3
2
1
0
Bit:
MSK data
transfer
Programming
Flag
Tx MSK end
Rx 2400b/s
Rx 1200b/s
Rx data information
required
This word holds the current status of the CMX881: the value read out is only valid when bit 5 of the Power
Down Control register ($C0) is set to '1'. Changes in the Status register will cause the IRQ bit (bit 15) to
be set to '1' if the corresponding interrupt mask bit is enabled. An interrupt request is issued on the IRQN
pin when the IRQ bit is '1' and the IRQ MASK bit (bit 15 of register $CE) is set to '1'.
Bits 1 to 15 of the Status register are cleared to '0' after the Status register is read. Bit 0 is only cleared
by writing to the Programming Register.
Bits 14, 12 and 5 are reserved.
Bits 13, 11 and 10 indicate that a Selcall, CTCSS or DCS event caused the interrupt, the host should
then read the Tones Status register ($CC) for further information. In transmit these bits will be set to '0'.
Detection of the DCS turn off tone and removal of DCS turn off tone are both flagged as DCS events in
the Status register, not as CTCSS events.
Aux ADC High (bit 9) and Aux ADC Low (bit 8) reflect the recent history of the Aux ADC level, with
respect to the high and low thresholds. The most recent Aux ADC reading can be read from $B4.
Aux ADC
Aux ADC
Aux ADC history since last reading:
Neither threshold crossed
Monitor High Monitor Low
0
0
1
1
0
1
0
1
Signal gone below low threshold
Signal gone above high threshold
Signal gone below low threshold and above high
threshold
In Tx mode bit 7 will be set when the last bit of MSK data has been transmitted. Note; this bit will only be
set if bit 8 of the Tx Data register ($CA) is set at the appropriate time. In Rx mode this bit will be set to
'0'.
Bit 6 indicates that new transmit data is required (in Tx mode) or received data is ready to be read (in Rx
mode). For continuous transmission or reception of information, a data transfer should be completed
within the time appropriate for that data (see Table 9 Maximum Data Transfer Latency).
Bits 4 and 3 indicate the received data rate after a valid frame sync pattern has been detected. Bits 2
and 1 indicate the received frame sync pattern detected.
Data type
none
Bit 2 Bit 1 Received sync pattern:
Reserved
Bit 4 Bit 3
0
0
0
0
1
1
0
1
0
1
Reserved
SYNC
0
1
1200b/s
SYNT
SYND
2400b/s
1
1
0
1
Reserved
Reserved
Programming Flag, bit 0: The Programming Register ($C8) should only be written to when bit 0 is set to
'1' (with both Mode select bits set low – See register $C8). Writing to the Programming Register ($C8)
clears bit 0 to '0'. Bit 0 is restored to '1' when the programming action is complete, normally within 250µs,
when it is then safe to write to the Programming Register.
2004 CML Microsystems Plc
39
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
