PMR Signalling Processor
CMX881
1.7 Application Notes
Radio Section
Receive
Discriminator
input
FFSK
Audio output
Rx
Voice+SubAudio
Demodulator
CMX881
RF
M odulator
output 1
Audio input 1
Audio input 2
2-point Tx
Modulator
Transmit
MIC 1
MIC 2
M odulator
output 2
FFSK
Voice+SubAudio
Host
MicroController
Data Port
Keypad
Figure 13 Possible PMR Configuration
CRC and Parity information
1.7.1
15 bit CRC is used with the inbuilt data packeting with the following generator polynomial:
x15 + x14+ x13+ x11+ x4+ x2 + x0
A 15 bit remainder is calculated for previous bytes sent. When the CMX881 is instructed to send the
CRC these 15 bits are added onto the end of the message with the least significant bit inverted.
The 16th bit of the checksum is an even parity bit calculated from the message data and 15 bit CRC result
(including the inverted last bit of the CRC).
In receive the 15 bit CRC is calculated and even parity is generated at each byte boundary. If the
calculated receive CRC is zero and the parity bits match the CRC bit is set to indicate a correctly
decoded message.
2004 CML Microsystems Plc
47
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
