PMR Signalling Processor
CMX881
0
1.6.18
Bit:
$C5 RX DATA: 16-bit read-only
15
14
13
12
11
10
9
8
0
7
6
5
4
3
2
1
Rx
0
0
0
0
0
0
Rx Data Byte
CRC
Bits 15 to 10 and 8 are reserved.
Rx CRC (bit 9) indicates the validity of the received data bytes since the En CRC bit has been set, a ‘1’
indicates a valid CRC and parity bit, a ‘0’ indicates that the received CRC and parity bits do not match the
locally calculated values - see section 1.5.5.
Rx Data Byte (bits 7 to 0) holds the most recent byte of decoded MSK data. Received data is
continuous, if the data is not read before the next data is received the current data will be over-written.
1.6.19
$CC TONES STATUS: 16-bit read-only
15
14
13
12
11
10
9
8
7
0
6
0
5
4
3
2
1
0
Bit:
Detected Selcall tone frequency
Sub-Audio Status
Detected CTCSS code
This word holds the current status of the CMX881 sub-audio and Selcall sections. This word should be
read by the host after an interrupt caused by a DCS, CTCSS or Selcall event.
The value in bits 5 to 0, Detected CTCSS code, identifies the detected sub-audio tone by its position in
Table 2 CTCSS Tones. If bits 5 to 0 = '000000' there is no CTCSS tone currently being detected. If bits
5 to 0 = '110111' (= 55 in decimal) this indicates that an Invalid Tone has been detected. An Invalid
Tone is any tone in the subaudio band which is not the selected subaudio tone. A change in the state of
bits 5-0 to Invalid Tone from the no tone condition will not cause Status register ($C6), b11 to be set to
'1'. Any other change in the state of bits 5-0 will cause the Status register ($C6), b11 to be set to '1'.
A detected Selcall frequency is indicated by the value in bits 15 to 11, ‘Detected Selcall tone frequency’,
identifies the frequency by its position in Table 5 Selcall Tones. If bits 15 to 11 = '00000' there is no
Selcall tone currently being detected. A change in the state of bits 15 to 11 will cause bit 13 of the Status
register ($C6), ‘Selcall State Change’, to be set to '1'.
Bits 10 to 8 indicate the DCS and special sub-audio tone status. The Status register ($C6) will indicate
the type of signal detected. If DCS or special CTCSS tones are detected they will be indicated in bits 10
to 8 according to the table below and bits 5 to 0 will be set to '000000'. If a normal CTCSS tone is
detected bits 10 to 8 will be set to '000' and bits 5 to 0 will indicate the decoded tone. A change in the
state of bits 10 to 8 will cause the DCS state change bit of the Status register to be set to '1'. During DCS
receive, the device can flag an interrupt when the DCS code fails to be recognised. This may be due to
code dropout. The turn off tone may be flagged shortly after, if the transmission is ending. Alternatively
the DCS link may be restored and DCS detection will be flagged again.
Bit 10 Bit 9 Bit 8
Sub-Audio status
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No DCS or special CTCSS detected
Reserved
DCS sequence detected
inverted DCS sequence detected
Reserved
Only enabled with DCS
Only enabled with DCS
134.4Hz DCS turn off tone detected
Reserved
Only enabled with DCS
Reserved
When the relevant detection mode is not enabled, the associated bits will be set to '0'. In Tx mode this
register will be set to '0'.
Bits 7 and 6 are reserved.
During DCS receive, the device can flag an interrupt when the DCS code fails to be recognised. This
may be due to code dropout. The turn off tone may be flagged shortly after, if the transmission is ending.
Alternatively the DCS link may be restored and DCS detection will be flagged again.
2004 CML Microsystems Plc
40
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
