PMR Signalling Processor
CMX881
0
1.6.12
$C8 PROGRAMMING REGISTER: 16-bit write-only
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
First
Block
Block /
Programming Data
Word
Number
Data
See section 1.6.20 for a description of this register.
1.6.13
Bit:
$CA TX DATA: 16-bit write-only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
En
Tx
Last
0
0
0
0
0
Tx Data Byte
CRC CRC Data
Bits 15 to 11 are reserved, set to '0'.
Bits 10 to 8 control the MPT1327 compatible CRC / parity circuit: See section 1.5.5 for timing diagrams.
En CRC (bit 10):
Tx: This bit should be changed when updating this register with new data. If this bit is set to '0' the CRC /
parity circuit will be reset, bits 7 to 0 will be passed to both the modulator and CRC / parity circuit
after it has been reset. If set to '1' the CRC / parity circuit will not be reset and bits 7 to 0 will be
passed to both the modulator and CRC / parity circuit.
Rx: In receive this bit should be changed before the interrupt for the next over-air byte occurs. If this bit
is set to '0' the next received byte will be passed to the CRC / parity circuit after it has been reset. If
this bit is set to '1' the next received byte will be passed to the CRC / parity circuit which will not be
reset.
Tx CRC (bit 9): If this bit is set to '1' the Tx Data Byte (bits 7-0) is transmitted and also passed to the
CRC and parity generator. The following 2 bytes transmitted are the 15 bits of CRC and the 1 bit of
parity. The request to load more data into the CMX881 will be raised after the 2nd byte is passed to the
modulator.
Last Data (bit 8): If this bit is set to '1' then the CMX881 will ignore bits 7 to 0, finish transmitting the
current byte, append a hang bit and then turn off the FFSK modulator. At the end of transmitting the
hang bit the CMX881 will set bit 7 of the Status register to '1' and an interrupt (if enabled) will be raised,
the host may then wait a short time before shutting down the rf sections of the transmit path.
Tx Data Byte (bits 7 to 0) holds the next byte of MSK data to be transmitted. Outgoing data is
continuous, whatever data is in bits 7 to 0 will be re-transmitted if the host does not provide required data
in time. Transmission of current data will be completed before transmission of newly loaded data begins.
1.6.14
$CD AUDIO TONE: 16-bit write only
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
0
0
0
0
Audio Tone
When the required bits of the Mode Control register ($C1) are set an audio tone will be generated with
the frequency determined by bits (11-0) of this register in accordance with the formula below:
frequency = Audio Tone (i.e. 1Hz per LSB)
If bits 11-0 are programmed with '0' no tone (i.e. Vbias) will be generated when the Audio Tone is
enabled. The Audio Tone frequency must only be set to generate frequencies from 300Hz to 3000Hz.
The host must suppress other data and set the correct audio routing before generating an audio tone and
re-enable data and audio routing on completion of the audio tone. The timing of intervals between these
actions is also controlled by the host µC.
This register may be written to whilst the audio tone is being generated, any change in frequency will
take place after the C-BUS write to this register. This allows sequences (e.g. ring or alert tunes) to be
generated for the local speaker (Tx or Rx via the AUDIO pin) or transmitted signal (via the MOD1/2 pins).
2004 CML Microsystems Plc
37
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
