PMR Signalling Processor
CMX881
8
1.6.15
Bit:
$CE INTERRUPT MASK: 16-bit write-only
15
14
13
12
11
10
9
IRQ
Rx Selcall
Rx CTCSS
Rx DCS
Aux ADC High Aux ADC Low
0
0
MASK
detect MASK
detect MASK detect MASK
MASK
MASK
7
6
5
0
4
3
2
0
1
0
0
Bit:
Tx MSK end Data transfer
MASK MASK
Rx 2400b/s
Rx 1200b/s
Prog Flag
MASK
detect MASK detect MASK
Bit
15
Value Function
1
0
Enable selected interrupts
Disable all interrupts (IRQN pin not activated)
Reserved – Set to 0
14
13
1
Enable interrupt when a change to a Selcall tone is detected as indicated
by a '0' to '1' change of bit 13 of the Status register
0
0
1
Disabled
Reserved - Set to 0
12
11
Enable interrupt when a change to a programmed CTCSS tone is
detected as indicated by a '0' to '1' change of bit 11 of the Status register
0
1
Disabled
10
Enable interrupt on a change in the detect status of the DCS decoder as
indicated by a '0' to '1' change of bit 10 of the Status register
0
1
0
1
0
1
0
0
1
0
1
0
0
1
Disabled
9, 8
7
Enable interrupt when the corresponding Aux ADC status bit changes
Disabled
Enable interrupt when MSK data transmission has ended
Disabled
6
Enable interrupt when an MSK data transfer is required
Disabled
Reserved - Set to 0
5
4
Enable interrupt when a valid 2400b/s frame sync is detected
Disabled
3
Enable interrupt when a valid 1200b/s frame sync is detected
Disabled
Reserved - Set to 0
2,1
0
Enable interrupt when Prog Flag bit of the Status register changes from '0'
to '1' (see Programming register $C8)
0
Disabled
The following 4 registers are read only
1.6.16 $B4 AUX ADC MONITOR DATA: 8-bit read-only
Bit:
7
6
5
4
3
2
1
0
Signal Monitor Data
This data holds the result of the last measurement performed by the auxiliary ADC.
The signal processor must be on to read Aux ADC data, so Power Down Control register b5 must be set
to ‘1’. This is independent of whether Tx or Rx modes are selected.
2004 CML Microsystems Plc
38
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
