PMR Signalling Processor
CMX881
1.6.8
$C1 MODE CONTROL: 16-bit write-only
15
14
13
12
11
10
9
8
0
Bit:
Enable
Voice
In band signalling:
Selcall, Tx DTMF
Generate
Enable
Enable DCS
Inverse
Enable DCS
Audio Tone
CTCSS
7
6
5
4
3
2
0
1
0
Bit:
Enable
Enable
SYNC
SYND
SYNT
Mode Select
2400b/s
1200b/s
Bits 1 and 0 control the overall mode of the CMX881 according to the table below:
Bit 1
Bit 0
Device Mode
0
0
1
1
0
1
0
1
Idle
Receive Mode
Transmit Mode
Reserved - do not use
During transmit, only one signal type may be enabled for each of the sub-audio and voice bands, see
Table 8. During receive the CMX881 will search for all signals enabled in this register and report those
that are successfully decoded. See also Table 1 in section 1.5.3.
In transmit mode the CMX881 begins transmission of a selected signal immediately after it has been
enabled. The host µC must ensure all associated data and control bits have been set to their required
values before enabling the signal in this register.
Bits 4 and 3 control the modem functions of the CMX881 in accordance with the following table:
Bit 4 Bit 3
Tx - Transmitted signal
Rx - Monitored signal(s)
0
0
1
1
0
1
0
1
None
None
MSK 1k2b/s
MSK 2k4b/s
Reserved
MSK 1k2b/s
MSK 2k4b/s
MSK 1k2 & 2k4b/s
In transmit mode data transmission will start or finish (regardless of whether all data has been
transmitted) immediately after the modem control bits are changed. To transmit a second data message
the modem control bits must be set to '0', data bytes for the following message loaded, and the required
bits set to '1'.
When MSK receive is enabled bits 5 to 7 allow the detection of the MSK SYND, SYNC and SYNT frame
sync patterns respectively. Each frame sync pattern may be individually controlled so any combination
of the 3 patterns - SYND, SYNC (and it's inverse - SYNT) can be searched for. When transmitting MSK
these bits should be set to '0' and the bit sync and frame sync patterns set in the first four 8 bit transfers
from the host - see section 1.5.5.
Bits 2 and 8 are reserved - set to '0'.
2004 CML Microsystems Plc
34
D/881/7
CMLMICRO [ CML MICROCIRCUITS ]
