TDMA Digital Radio Processor
CMX7161
To reduce overhead some C-BUS read and write registers are capable of streaming operation. This allows
multiple read or write data words to follow a single address byte all within the same C-BUS transaction.
C-BUS data-streaming (8-bit write register)
CSN
SCLK
CDATA
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Last byte
Address
First byte
Second byte
…
Hi-Z
RDATA
C-BUS data-streaming (8-bit read register)
CSN
SCLK
CDATA
7 6 5 4 3 2 1 0
Address
Hi-Z
RDATA
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Last byte
First byte
Second byte
…
Data value unimportant
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Figure 9 C-BUS Data Streaming Operation
Notes:
1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset)
2. For single byte data transfers only the first 8 bits of the data are transferred
3. The CDATA and RDATA lines are never active at the same time. The address byte determines
the data direction for each C-BUS transfer.
4. The SCLK can be high or low at the start and end of each C-BUS transaction
5. The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are
optional, the host may insert gaps or concatenate the data as required.
2013 CML Microsystems Plc
Page 17
D/7161_FI-1.0/4
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