TDMA Digital Radio Processor
CMX7161
6
General Description
CMX7161 FI-1.x is a half-duplex digital radio modem intended for use in two-slot TDMA systems such as
the ETSI TS 102 361 standard for Digital Mobile Radio (DMR). It uses root-raised-cosine (=0.2) 4-FSK
modulation in a 12.5kHz channel. Slot timing and synchronisation are handled automatically by the device.
An integrated analogue interface supports direct connection to an I/Q receiver and two-point modulation
transmitter with few external components; no external codecs are required.
Intelligent auxiliary ADC, DAC and GPIO sub-systems are provided to minimise required host interaction
and host I/O resources. Two synthesised system clock generators develop clock signals for off-chip use.
The C-BUS/SPI master interface expands host C-BUS/SPI ports to control external devices.
The CMX7161 operates from a 3.3V supply and is available in 64-VQFN and 64-LQFP packages.
The device uses CML’s proprietary FirmASIC component technology. On-chip sub-systems are
configured by a Function Image™ data file which is uploaded during device initialisation to define the
device's function and feature set. The Function Image™ can be loaded automatically from a host µC over
the C-BUS serial interface or from an external memory device. The device's functions and features can be
enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
The device includes provision for an external oscillator, with phase locked loop and buffered output, to
provide a System Clock output, if required, for other devices. Block diagrams of the device are shown in
Section 2, Block Diagrams.
Tx Functions:
Two-point modulation analogue outputs
Root-raised-cosine (=0.2) pulse shaping
RAMDAC capability for PA ramping control
Tx trigger feature allowing precise control of burst start time
Tx burst sequence for automatic RAMDAC ramping and hardware switching
Rx Functions:
I/Q analogue inputs
Rx channel filtering and root-raised-cosine (=0.2) pulse shaping
Data returned as hard-decision bits or 4-bit soft-decision LLR metrics
Automatic frame sync detection simplifies host control
Automatic tracking of symbol timing and input I/Q DC offsets
Received Signal Strength Indicator
Slot timing functions:
30ms slot format (264-bit bursts)
Internal slot clock and timing maintenance
Automatic synchronisation to received channel
Automatic sequencing of hardware control
Auxiliary Functions:
Two programmable system clock outputs
Four auxiliary ADCs with six selectable input paths
SPI Thru-Port for interfacing to synthesisers and other serially controllable devices
Four auxiliary DACs, one with built-in programmable RAMDAC
Tx Enable and Rx Enable
Host Interface:
Optimised C-BUS (4-wire, high speed synchronous serial command/data bus) interface to host for
control and data transfer, including streaming C-BUS for efficient data transfer
Open drain IRQ to host
Two GPIO pins
Serial memory or C-BUS (host) boot mode.
2013 CML Microsystems Plc
Page 14
D/7161_FI-1.0/4
CMLMICRO [ CML MICROCIRCUITS ]
