TDMA Digital Radio Processor
CMX7161
7
Detailed Descriptions
External Oscillator Frequency
7.1
The CMX7161 is designed to work with an external oscillator at 19.2MHz with a frequency tolerance of
0.5ppm.
7.2
Radio Interface
The CMX7161 supports direct connection to a direct conversion receiver such as the CML CMX994 and a
two-point modulation transmitter. No external RF codecs are required. An example outline radio design is
shown in Figure 7.
HOST
uP
GPIOA (Rx Enable), GPIOB (Tx Enable)
CMX7161
A
B
C
D
GPIO
I INPUT
LNA
Tx / Rx
I
Channel
/6 /4
or /2
2 x ADC
Q INPUT
4
CMX994
C-BUS
Control
Interface
Q
Channel
Thru C-BUS
2 x DAC
/6 /4
/2 /1
PLL
VCO
1
RAMDAC
(Aux DAC1)
PA Gain Control
Reference
(e.g VCTCXO)
MOD1
MOD2
PLL
Control
Voltage
Input
VCO
Power Amplifier
Figure 7 Outline Radio Design
7.3
Host Interface
The primary interface for commands, status information and payload data transfer from the host µC
consists of a bank of device registers addressed and accessed using a serial data interface (C-BUS). The
C-BUS interface is hardware compatible with Microwire™, SPI™ and other similar interfaces.
A dedicated interrupt line to the host µC is also provided to alert the host µC to significant events.
Interrupts of different types can be individually enabled using the IRQ Mask Register ($6C read) and the
cause of each interrupt is reported in the IRQ Status Register ($7E read).
7.3.1 C-BUS Operation
C-BUS transactions consist of an address byte sent from the µC followed by zero or more data byte(s)
written into or read out from the register that has been addressed. Note that registers are either writable or
readable, but not both.
C-BUS registers are 8 or 16 bits wide, and most transactions therefore involve one or two data bytes.
Some registers also support streaming transactions in which a single register address byte is followed by
many data bytes being written to or read from the CMX7161.
Certain C-BUS transactions require only an address byte to be sent from the µC with no data transfer. This
includes the General Reset command.
2013 CML Microsystems Plc
Page 15
D/7161_FI-1.0/4