TDMA Digital Radio Processor
CMX7161
Data sent from the µC on the CDATA (command data) line is clocked into the CMX7161 on the rising edge
of the SCLK input. Data sent from the CMX7161 to the µC on the RDATA (reply data) line is valid when
SCLK is high. The CSN line must be held low during a data transfer and kept high between transfers. The
C-BUS interface is compatible with most common µC serial interfaces and may also be easily
implemented with general purpose µC I/O pins controlled by a simple software routine.
7.3.2 C-BUS Timing
C-BUS single byte command (no data)
CSN
Note:
The SCLK line may be high or
low at the start and end of each
transaction.
SCLK
CDATA
7
MSB
6
5
4
3
2
2
2
1
1
1
0
LSB
Address
Hi-Z
RDATA
C-BUS n-bit register write
CSN
SCLK
CDATA
RDATA
7
MSB
6
5
4
3
0
LSB
n-1 n-2 n-3
2
1
0
MSB
LSB
Address
Write data
Hi-Z
C-BUS n-bit register read
CSN
SCLK
CDATA
RDATA
7
MSB
6
5
4
3
0
LSB
Address
Hi-Z
n-1 n-2 n-3
2
1
0
MSB
LSB
Read data
Data value unimportant
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Figure 8 Basic C-BUS Transactions
2013 CML Microsystems Plc
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