Digital PMR Radio Processor
CMX7131/CMX7141
The frequency for each synthesiser is set by using two registers: an ‘R’ register that sets the division value
of the input reference frequency to the comparison frequency (step size), and an ‘N’ register that sets the
division of the required synthesised frequency from the external VCO to the comparison frequency. This
yields the required synthesised frequency (Fs), such that:
Fs = (N / R) x FREF
where FREF is the selected reference frequency.
Other parameters for the synthesisers are the charge pump setting (high or low).
Since the set-up for the PLLs takes 4 x “RF Channel Data register” writes it follows that, while updating the
PLL settings, the registers may contain unwanted or intermediate values of bits. These will persist until the
last register is written. It is intended that users should change the content of the “RF Channel Data
register” on a PLL that is disabled, powersaved or selected to work from the alternate register set (“Tx”
and “Rx” are alternate register sets). There are no interlocks to enforce this intention. The names “Tx” and
“Rx” are arbitrary and may be assigned to other functions as required. They are independent sets of
registers, one of which is selected to command each PLL by changing the settings in the RF Synthesiser
Control (CMX7131 only) - $B3 write register.
For optimum performance, a common master clock should be used for the RF synthesisers (RFClock) and
the baseband sections (Main and Auxiliary System Clocks). Using unsynchronised clocks can result in
spurious products being generated in the synthesiser output and in some cases difficulty may be
experienced with obtaining lock in the RF synthesisers.
Lock Status
The lock status can be observed by reading the RF Channel Status register, $B4, and the individual lock
status bits can (subject to masking) provide a C-BUS interrupt.
The lock detector can use a tolerance of one cycle or four cycles of the reference clock (not the divided
version that is used as a comparison frequency) in order to judge phase lock. An internal shift register
holds the last three lock status measurements and the lock status bits are flagged according to a majority
vote of these previous three states. Hence, one occasional lock error will not flag a lock fail. At least two
successive phase lock events are required for the lock status to be true. Note that the lock status bits
confirm phase lock to the measured tolerance and not frequency lock. The synthesiser may take more
time to confirm phase lock with the lock status bits than the time to switch from channel to channel. The
purpose of a 4-cycle tolerance is for the case where a high frequency reference oscillator would not
tolerate a small phase error.
RF Inputs
The RF inputs are differential and self-biased (when not powersaved). They are intended to be
capacitatively coupled to the RF signal. The signal should be in the range 0dBm to –20dBm (not
necessarily balanced). To ensure an accurate input signal the RF should be terminated with 50Ω as close
to the chip as possible and with the “N” and “P” inputs capacitively coupled to the input and ground,
keeping these connections as short as possible. The RF input impedance is almost purely capacitative
and is dominated by package and printed circuit board parasitics.
Guidelines for Using the RF Synthesisers
RF input slew rate (dv/dt) should be 14V/µs minimum
The RF synthesiser 2.5V digital supply can be powered from the VDEC output pin
RF clock sources and other, different clock sources must not share common IC components, as this
may introduce coupling into the RF. Unused ac-coupled clock buffer circuits should be tied off to a dc
supply, to prevent them oscillating
It is recommended that the RF synthesisers are operated with maximum gain (i.e. ISET1/2 tied to
RFV
)
SS
The loop filter components should be optimised for each VCO
2014 CML Microsystems Plc
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CMLMICRO [ CML MICROCIRCUITS ]
