Digital PMR Radio Processor
CMX7131/CMX7141
The CMX7131/CMX7141 defaults to the settings appropriate for a 19.2MHz oscillator, however if other
frequencies are to be used then the Program Block registers P3.2 to P3.6 will need to be programmed
appropriately at power-on. This flexibility allows the device to re-use an external clock source, so reducing
total cost and potential noise sources. A table of common values is provided in Table 9.
See:
o
Program Block 3 – AuxDAC, RAMDAC and Clock Control
6.12.2 System Clock Operation
Two System Clock outputs, SYSCLK1 and SYSCLK2, are available to drive additional circuits, as required.
These are digital phase locked loop (PLL) clocks that can be programmed via the System Clock registers
with suitable values chosen by the user. The System Clock PLL Configure registers ($AB and $AD) control
the values of the VCO Output divider and Main Divide registers, while the System Clock Ref. Configure
registers ($AC and $AE) control the values of the Reference Divider and signal routing configurations. The
PLLs are designed for a reference frequency of 96kHz. If not required, these clocks can be independently
powersaved. The clock generation scheme is shown in the block diagram of Figure 26. Note that at power-
on, these pins are disabled.
o
o
See:System CLK 1 and 2 PLL data - $AB, $AD write
System CLK 1 and 2 REF - $AC and $AE write
6.13 Signal Level Optimisation
The internal signal processing of the CMX7131/CMX7141 will operate with wide dynamic range and low
distortion only if the signal level at all stages in the signal processing chain is kept within the recommended
limits. For a device working from a 3.3V ±10% supply, the maximum signal level which can be
accommodated without distortion is [(3.3 x 90%) - (2 x 0.3V)] volts pk-pk = 838mVrms, assuming a sine
wave signal. This should not be exceeded at any stage.
6.13.1 Transmit Path Levels
For the maximum signal out of the MOD1 and MOD2 attenuators, the signal level at the output of the
Modem block is set to be 0dB, The Fine Output adjustment ($C3) has a maximum attenuation of 1.8dB
and no gain, whereas the Coarse Output adjustment ($B0) has a variable attenuation of up to 12.0dB and
no gain.
6.13.2 Receive Path Levels
The Coarse Input adjustment ($B1) has a variable gain of up to +22.4dB and no attenuation. In LD mode,
with the lowest gain setting (0dB), the maximum allowable input signal level at the DISCFB pin would be
838mVrms. This signal level is an absolute maximum, which should not be exceeded.
In I/Q mode CMX7131/CMX7141 automatically manages the gain control settings to optimise signal levels.
2014 CML Microsystems Plc
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