Digital PMR Radio Processor
CMX7131/CMX7141
6.12 Digital System Clock Generators
to RF Synthesiser
Ref CLK selection
SysCLK1 VCO
24.576-
98.304MHz
LPF
VCO
VCO
VCO
(49.152MHz typ)
Ref CLK div
/1 to 512
PLL div
/1 to 1024
$AB b0-9
PD
SysCLK1
Ref
SysCLK1
Div
$AC b0-8
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
$AB b10-15
SysCLK1
Pre-CLK
$AC b11-15
SysCLK1
Output
384kHz - 20MHz
SysCLK2 VCO
24.576 -98.304 MHz
(49.152MHz typ)
LPF
Ref CLK div
/1 to 512
PLL div
/1 to 1024
$AD b0-9
PD
SysCLK2
Ref
SysCLK2
Div
$AE b0-8
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
$AD b10-15
SysCLK2
Pre-CLK
$AE b11-15
SysCLK2
Output
384kHz - 20MHz
MainCLK VCO
24.576-
LPF
98.304MHz
(49.152MHz typ)
Ref CLK div
/1 to 512
P3.4
PLL div
/1 to 1024
P3.5
PD
MainCLK
Ref
MainCLK
Div
48 - 192kHz
(96kHz typ)
VCO op div
/1 to 64
P3.3 & 3.6
MainCLK
Output
MainCLK
Pre-CLK
384kHz - 50MHz
(24.576MHz typ)
To Internal
ADC / DAC
dividers
3.0 - 12.288 MHz Xtal or
3.0 - 24.576 MHZ Clock
OSC
AuxADC
Div
P3.3 & P3.6
Aux_ADC
(83.3kHz typ)
Figure 26 Digital Clock Generation Schemes
The CMX7131/CMX7141 includes a two-pin crystal oscillator circuit. This can either be configured as an
oscillator, as shown in section 4.2, or the XTAL input can be driven by an externally generated clock. The
crystal (Xtal) source frequency can go up to 12.288MHz (clock source frequency up to 24.576MHz), but a
19.2MHz oscillator is assumed by default for the functionality provided in the CMX7131/CMX7141.
6.12.1 Main Clock Operation
A digital PLL is used to create the Main Clock (nominally 24.576MHz) for the internal sections of the
CMX7131/CMX7141. At the same time, other internal clocks are generated by division of either the XTAL
Reference Clock or the Main Clock. These internal clocks are used for determining the sample rates and
conversion times of A-to-D and D-to-A converters, running a General Purpose Timer and the signal
processing block. In particular, it should be noted that in Idle mode the setting of the GP Timer divider
directly affects the C-BUS latency (with the default values this is nominally 250μs).
2014 CML Microsystems Plc
Page 58
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CMLMICRO [ CML MICROCIRCUITS ]
