Digital PMR Radio Processor
CMX7131/CMX7141
threshold or a falling edge passes the low threshold, see Figure 23 and AuxADC Configuration - $A7 write
register. The thresholds are programmed via the Aux Config - $CD write register.
IRQ
IRQ
IRQ
IRQ
High
Threshold
Signal
Low
Threshold
Figure 23 AuxADC IRQ Operation
Auxiliary ADC data is read back in the AuxADC Data registers ($A9 and $AA) and includes the threshold
status as well as the actual conversion data (subject to averaging, if enabled).
See:
o
o
o
o
AuxADC Configuration - $A7 write
AuxADC1 Data and Threshold Status - $A9 read
AuxADC2 Data and Threshold Status - $AA read
Aux Config - $CD write
6.10 Auxiliary DAC/RAMDAC Operation
The four auxiliary DAC channels are programmed via the AuxDAC Control register, $A8. AuxDAC channel
1 may also be programmed to operate as a RAMDAC which will automatically output a pre-programmed
profile at a programmed rate. The AuxDAC Control register, $A8, with b12 set, controls this mode of
operation. The default profile is a raised cosine (see Table 20), but this may be over-written with a user-
defined profile by writing to Programming register P3.11. The RAMDAC operation is only available in Tx
mode and, to avoid glitches in the ramp profile, it is important not to change to Idle or Rx mode whilst the
RAMDAC is still ramping. The AuxDAC outputs hold the user-programmed level during a powersave
operation if left enabled, otherwise they will return to zero. Note that access to all four AuxDACs is
controlled by the AuxDAC Control register, $A8, and therefore to update all AuxDACs requires four writes
to this register. It is not possible to simultaneously update all four AuxDACs.
See:
o
AuxDAC Data and Control - $A8 write
2014 CML Microsystems Plc
Page 54
D/7141_FI-3.x/6
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