Digital PMR Radio Processor
CMX7131/CMX7141
6.7 Squelch Operation
Many Limiter/Discriminator chips provide a noise-quieting squelch circuit around an op-amp configured as
a filter. This signal is conventionally passed to a comparator to provide a digital squelch signal, which can
be routed directly to one of the CMX7131/CMX7141’s GPIO pins or to the host. However with the
CMX7131/CMX7141, the comparator and threshold operations can be carried out by one of the AuxADCs
with programmable thresholds and hysteresis functions.
See:
o
o
IRQ Status - $C6 read
AuxADC Configuration - $A7 write
Note: This functionality is not necessary in I/Q mode as squelch detection is within CMX7131/CMX7141
signal processing however the AuxADC functionality remains available.
6.8 GPIO Pin Operation
The CMX7131/CMX7141 provides four GPIO pins: GPIO1, GPIO2, GPIOA and GPIOB. RXENA (GPIO1)
and TXENA (GPIO2) are configured to reflect the Tx/Rx state of the Mode register (TXENA and RXENA,
active low).
See:
o
Modem Control - $C1 write
Note that TXENA and RXENA will not change state until the relevant mode change has been executed by
the CMX7131/CMX7141. This is to allow the host sufficient time to load the relevant data buffers and the
CMX7131/CMX7141 time to encode the data required prior to its transmission. There is thus a fixed time
delay between the GPIO pins changing state and the data signal appearing at the MOD output pins.
During the power-on sequence (until the FI has completed its load sequence) these pins have only a weak
pull-up applied to them so care should be taken to ensure that any loading during this period does not
adversely affect the operation of the unit.
GPIOA and GPIOB are host programmable for input or output using the AuxADC Configuration register,
$A7. The default state is input, with a weak pullup resistor. When set for input the values can be read back
using the Modem Status register, $C9.
6.9 Auxiliary ADC Operation
The inputs to the two auxiliary ADCs can be independently routed from any of the signal input pins under
control of the Signal Routing register, $A7. Conversions will be performed as long as a valid input source
is selected, to stop the ADCs, the input source should be set to “off”. Register $C0, b6, BIAS, must be
enabled for auxiliary ADC operation.
Averaging can be applied to the AuxADC readings by selecting the relevant bits in the AuxADC
configuration register, $A7, the length of the averaging is determined by the value in the Program Block
(P3.0 and P3.1), and defaults to a value of 0. This is a rolling average system such that a proportion of the
current data will be added to the last average value. The proportion is determined by the value of the
average counter in P3.0 and P3.1.
For an average value of:
0 = 50% of the current value will be added to 50% of the last average value,
1 = 25% of the current value will be added to 75% of the last average value,
2 = 12.5% etc.
The maximum useful value of this field is 9.
High and low thresholds may be independently applied to both AuxADC channels (the comparison is
applied after averaging, if this is enabled) and an IRQ generated when a rising edge passes the high
2014 CML Microsystems Plc
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