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CMX7131Q1 参数 Datasheet PDF下载

CMX7131Q1图片预览
型号: CMX7131Q1
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 4MHz, CMOS, VQFN-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 4034 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Digital PMR Radio Processor  
CMX7131/CMX7141  
6.5.7 Tx Mode PRBS  
In PRBS mode ($C1, Modem Control = $0032) the preamble and frame sync are transmitted automatically  
followed by a PRBS pattern conforming to ITU-T O.153 (para. 2.1) giving a 511-bit repeating sequence.  
6.5.8 Tx Mode Preamble  
In Preamble mode ($C1, Modem Control = $0042) the preamble sequence [+3 +3 -3 -3] is sent continually.  
This can be used to set up and adjust the RF hardware.  
6.5.9 Tx Mode Mod Set-up  
In Mod Set-up mode ($C1 = $0052) the output depends on the selected Tx modulation type. In two-point  
mode, a repeating sequence of eight +3 symbols followed by eight -3 symbols is sent, and in I/Q mode a  
continuous sequence of +3 symbols is sent. This can be used to set up and adjust the RF hardware.  
6.5.10 Tx Mode Repeated Word  
In Repeated Word mode ($C1 = $0062) the preamble and frame sync are transmitted automatically  
followed by the data provided by the host in TxData4. This feature allows the NXDN standard test  
waveforms to be transmitted as part of the test and qualification procedures.  
6.5.11 Tx Sequencer  
The Tx Sequencer provides an automated way of executing a sequence of actions, thus reducing timing  
constraints placed on the host. It is controlled by setting b15 in the Modem Configuration register ($C7) to  
1. If enabled, it will automatically start executing its sequence of transmit actions when the  
CMX7131/CMX7141 is placed in Tx mode. The timing values for each action can be set in P3.75 to P3.79  
and are defined in increments of 250µs.  
The duration of the ramp by the RAMDAC is controlled by P3.80 The RAMDAC scan time configuration.  
It can be configured to ramp over a period of between 80µs and 32ms.  
On expiry of the Tx ENA inactive delay the CMX7131/CMX7141 will return to the previous operating mode  
automatically. It will also assert the “EndOfSequence” IRQ to the host at this point ($C6:b2 =1), signalling  
that the Tx sequence has completed.  
C-BUS latency delay  
(10 260us)  
CSN  
Tx_ENA  
P3.75  
P3.79  
Tx_ENA active  
Tx_ENA inactive  
DAC1  
RAMDAC  
P3.76  
RAMDAC Up delay  
P3.78  
RAMDAC Down Delay  
MOD1  
Modulation  
P3.77  
Modulation Start Delay  
End Of  
Sequence  
Tx Done  
Figure 20 Automatic Tx Sequencer  
2014 CML Microsystems Plc  
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