Digital PMR Radio Processor
CMX7131/CMX7141
21. Wait for DataReady IRQ
22. …repeat from 12 with the SACCH data set appropriately
23. Load TxData registers with LICH (7 bits) and SACCH (26 bits) for “Clearing”
24. Wait for DataReady IRQ
25. Load TxData registers with FACCH1 data (40 bits)
26. Wait for DataReady IRQ
27. Load TxData registers with FACCH1 data (40 bits)
28. Wait for DataReady IRQ.
29. Load TxData registers with FACCH1 data (40 bits)
30. Wait for DataReady IRQ
31. Load TxData registers with FACCH1 data (40 bits)
32. Wait for DataReady IRQ.
After the last data bit has left the modulator a “TxDone” IRQ will be asserted. At this point it is now safe for
the host to change the Modem Control and Modem Mode to IDLE ($C1, Modem Control = $0000) and turn
the RF transmitter off.
A typical host Tx sequence for Data Communications is:
1. Load TxData registers with LICH (7 bits) for “10 01 11 0”
2. Set Modem Control = TxFormat, Modem Mode = Tx
3. (Device will start transmission of Preamble and SW followed by contents of TxData registers)
4. Wait for DataReady IRQ
5. Load TxData registers with first part of UDCH1 (72 bits) – this includes the SU field
6. Wait for DataReady IRQ
7. Load TxData registers with second part of UDCH1 (72 bits)
8. Wait for DataReady IRQ
9. Load TxData registers with third part of UDCH1 (40 bits)
10. Wait for DataReady IRQ
11. Load TxData registers with LICH (7 bits) for “10 01 11 0”
12. …repeat from 4
13. Load TxData registers with LICH (7 bits) for “10 01 01 0”
14. Wait for DataReady IRQ
15. Load TxData registers with FACCH2 data (72 bits)
16. Wait for DataReady IRQ
2014 CML Microsystems Plc
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