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CMX608 参数 Datasheet PDF下载

CMX608图片预览
型号: CMX608
PDF下载: 下载PDF文件 查看货源
内容描述: [Integrated Input and Output Channel Filters]
分类和应用:
文件页数/大小: 70 页 / 3411 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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RALCWI Vocoder  
CMX608/CMX618/CMX638  
5.10.4.  
16-bit Write-Only Registers  
VCTRL register address $11 (also MVCTRL register address $3C)  
15  
0
14  
0
13  
ESTDP  
12  
ESTDD  
11  
EDTMFD  
10  
0
9
8
DSTDP  
DSTDG  
7
6
5
4
3
2
1
0
DSTDD  
DDTMFG DDTMFD  
DVDW  
PLC  
FECLOOP  
ENC  
DEC  
This write-only register controls the Vocoder when it is operating. A change in the state of these  
bits may take up to 20ms before any effect is observed. The VCTRL register is mirrored by the  
MVCTRL register ($3C). This read-only register holds the last value written to the VCTRL ($11)  
register. The MVCTRL register is updated before the value is validated and therefore may be  
used as confirmation that a write command to a 16-bit C-BUS register is working.  
After the VCTRL command has completed, bit 15 of the STATUS register ($40) will be set to '1'  
and, if enabled, IRQN will go low. No other C-BUS registers should be read or written whilst this  
command is in progress.  
Bit 0  
DEC  
Decoder Enable: If this bit is set to '1' the device will accept frames of vocoded  
audio, decode them, and send the samples to the D/A converter. If this bit is  
cleared to '0', any supplied frames will be ignored.  
Bit 1  
ENC  
Encoder Enable: If this bit is set to '1' the device will collect samples from the A/D  
converter, encode them and send the vocoded frames to the streaming  
ENCFRAME register ($30). If this bit is cleared to '0', no vocoded frames of audio  
will be produced.  
Note: Setting both DEC and ENC to '1' is the same as setting them both to' '0, as full duplex  
operation is not possible with the CMX608/CMX618. In the CMX638, DEC and ENC bits can be  
set as above, for half-duplex operation, or both DEC and ENC should be set to '1' for full-duplex  
operation. When operating in full-duplex, neither DTMF nor STD functions are supported.  
Bit 2  
FECLOOP  
Repeater Function Enable: If this bit is set to '1' the device will re-apply FEC to the  
previously supplied FEC encoded frame, after error correction, and then send it to  
the streaming ENCFRAME register ($30). This allows the device to be used in a  
repeater. If this bit is cleared to '0', this function is turned off.  
This bit is ignored if the ENC bit is set to '1'. If the DEC bit is set to '1', the  
supplied frames will also be decoded and sent to the D/A converter.  
Bit 3  
PLC  
Packet Loss Concealment (PLC): If this bit is set to '1' the device’s decoder will  
attempt to conceal badly corrupted frames by using a special PLC procedure. If  
this bit is cleared to '0', PLC will not be done.  
Bit 4  
DVDW  
Vocoder Data Wanted: If this bit is set to '1', the device will indicate that it is able  
to accept another Vocoder frame for decoding, by setting the VDW bit (bit 8) in  
the STATUS register ($40). If this bit is cleared to '0', this function is disabled.  
2014 CML Microsystems Plc  
46  
D/608_18_38/11  
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