RALCWI Vocoder
CMX608/CMX618/CMX638
When running the Vocoder in full-duplex mode (CMX638 only), the last bit of the data to be
decoded should be clocked into the device no later than 6ms after the VDA bit is set and (if
enabled) the corresponding IRQN is generated. This will ensure that the decoding and encoding
operations are scheduled correctly. Note that a C-BUS clock of at least 200kHz will be required in
streaming mode for transferring 80ms samples of soft decision encoded data. A higher C-BUS
clock speed is required if the data transfer is done a byte at a time.
The following table shows the frequency and packet size that needs to be written against the
configuration setting:
VCFG Register
Description of packet
DECFRAME
Byte Prod.
Count every
7
6
5
4
3
2
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
2400bps 1x20ms frame
2400bps 2x20ms frames
2400bps 3x20ms frames
2400bps 4x20ms frames
2750bps 1x20ms frame
2750bps 2x20ms frames
2750bps 3x20ms frames
2750bps 4x20ms frames
6
20ms
40ms
60ms
80ms
20ms
40ms
60ms
80ms
12
18
24
7
14
21
28
2400bps 3x20ms frames
with FEC / Hard bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
27
27
60ms
60ms
80ms
80ms
60ms
60ms
80ms
80ms
2750bps 3x20ms frames
with FEC / Hard bits
2400bps 4x20ms frames
with FEC / Hard bits
36
2750bps 4x20ms frames
with FEC / Hard bits
36
2400bps 3x20ms frames
with FEC / Soft bits
108
108
144
144
2750bps 3x20ms frames
with FEC / Soft bits
2400bps 4x20ms frames
with FEC / Soft bits
2750bps 4x20ms frames
with FEC / Soft bits
Table 6 Decoder Packet Description
This register is also used for loading blocks of Function Image™ data. Refer to section 6.7 for
further details.
2014 CML Microsystems Plc
43
D/608_18_38/11
CMLMICRO [ CML MICROCIRCUITS ]
