CPC75282
2.10 Thermal Shutdown
thermal shutdown mode will continue as long as the
fault condition persists. If the magnitude of the fault
condition is great enough, the external secondary
protector will activate, shunting the fault current to
ground.
The thermal shutdown mechanism activates when the
device die temperature reaches a minimum of 110°C,
placing the device in the All-Off state regardless of
logic input. During thermal shutdown events the T
SDx
pin will output a logic low with a nominal 0V level. A
logic high is output from the T pin during normal
2.11 External Protection Elements
SDx
operation with a typical output level equal to V
.
DD
The CPC75282 requires only over-voltage secondary
protection on the loop side of the device. The
integrated protection feature described above negates
the need for additional external protection on the SLIC
side. The secondary protector must limit voltage
transients to levels that do not exceed the breakdown
voltage or input-output isolation barrier of the
CPC75282. A foldback or crowbar type protector is
recommended to minimize stresses on the
CPC75282.
If presented with a short duration transient, such as a
lightning event, the thermal shutdown feature will
typically not activate. But in an extended power-cross
event, the device temperature will rise and the thermal
shutdown mechanism will activate forcing the switches
to the All-Off state. At this point the current measured
into T
or R
will drop to zero. Once the device
LINE
LINE
enters thermal shutdown, it will remain in the All-Off
state until the temperature of the device drops below
the de-activation level of the thermal shutdown circuit.
This permits the device to autonomously return to
normal operation. If the transient has not passed,
current will again flow up to the value allowed by the
dynamic DC current limiting of the switches and
heating will resume, reactivating the thermal shutdown
mechanism. This cycle of entering and exiting the
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces,” for equations related
to the specifications of external secondary protectors,
fused resistors, and PTCs.
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