CPC75282
2. Functional Description
2.1 Introduction
away from the SLIC via the protection diode bridge.
Power-cross potentials are also reduced by the current
limiting and thermal shutdown circuits.
The CPC75282 Dual LCAS device has six operating
states:
To protect the CPC75282 from an over-voltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the tip and ring terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC75282
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
• Idle/Talk: Break switches SW1 and SW2 closed,
ringing switches SW3 and SW4 open, and test
switches SW5 and SW6 open.
• Ringing: Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 open.
• Test: Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and loop test
switches SW5 and SW6 closed.
• Test/Monitor: Break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open, and
test switches SW5 and SW6 closed.
• Test Ringing: Break switches SW1 and SW2 open,
ringing switches SW3 and SW4 closed, and test
switches SW5 and SW6 closed.
• All-off: Break switches SW1 and SW2 open, ringing
switches SW3 and SW4 open, and test switches
SW5 and SW6 open.
The CPC75282 operates from a single +5V supply.
This gives the device extremely low idle and active
power consumption with virtually any range of battery
voltage. The battery voltage used by the CPC75282
has a two-fold function. For protection purpose it is
used as a fault condition current source during a
negative lightning event. Second, it is used as a
reference so that in the event of battery voltage loss,
the CPC75282 will enter the All-Off state.
See “Truth Tables” on page 11 for more information.
The CPC75282 offers break-before-make and
make-before-break switching from the ringing state to
the idle/talk state with simple logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ring
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State control is via
simple logic input so no additional driver circuitry is
required. The linear break switches, SW1 and SW2,
2.2 Under Voltage Switch Lock-Out Circuitry
Smart logic in the CPC75282 now provides for switch
state control during both power up and power loss
transitions. An internal detector is used to evaluate the
V
supply to determine when to de-assert the
DD
under-voltage switch lock-out circuitry with a rising
and when to assert the under-voltage switch
V
DD
lock-out circuitry with a falling V . Any time
DD
have exceptionally low R and excellent matching
ON
unsatisfactory low V conditions exist, the lock-out
DD
characteristics. The ringing switch, SW4, has a
minimum open contact breakdown voltage of 465V at
+25°C sufficiently high with proper protection to
prevent breakdown in the presence of a transient fault
condition (i.e., passing the transient on to the ringing
generator).
circuit overrides user switch control by blocking the
information at the external input pins, and conditioning
internal switch commands to the All-Off state. Upon
restoration of V , the switches will remain in the
DD
All-Off state until the LATCH input is pulled low.
x
The rising V lock-out release threshold is internally
DD
Integrated into the CPC75282 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection for the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
set to ensure all internal logic is properly biased and
functional before accepting external switch commands
from the input to control the switch states. For a falling
V
event, the lock-out threshold is set to assure
DD
proper logic and switch behavior up to the moment the
switches are forced off and external inputs are
suppressed.
12
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