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CPC75282KATR 参数 Datasheet PDF下载

CPC75282KATR图片预览
型号: CPC75282KATR
PDF下载: 下载PDF文件 查看货源
内容描述: 线卡接入交换机 [Line Card Access Switch]
分类和应用:
文件页数/大小: 19 页 / 667 K
品牌: CLARE [ CLARE ]
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CPC75282  
1.11 Truth Tables  
1.11.1 Operating States: CFG=0  
Break  
Switches  
Ringing  
Switches  
Test  
Switches  
1
State  
Idle/Talk  
P3  
P2  
P1  
OFF  
x
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
ON  
OFF  
OFF  
ON  
OFF  
OFF  
ON  
OFF  
ON  
Test  
1
1
1
1
1
1
1
Ringing  
OFF  
ON  
Test/Monitor  
Idle/Talk  
OFF  
OFF  
OFF  
ON  
ON  
OFF  
ON  
Test/Monitor  
Ringing  
ON  
OFF  
OFF  
OFF  
OFF  
ON  
Test Ringing  
ON  
2
All-Off  
OFF  
OFF  
0
1
P1, P2, and P3 data input values are directed to a given channel when the respective LATCH logic signal is set to “0.”  
x
OFF is a per-channel control.  
x
2
3
A “0” on OFF resets the CPC75282, the device will remain in the All-Off state until OFF is returned to “1” and the next LATCH signal is  
x
applied.  
x
x
CFG is fixed at D ; if CFG switches states when V is applied, the change will be recognized by a given channel after a LATCH low  
DD  
GND  
transition is applied to that channel.  
1.11.2 Operating States: CFG=1  
Break  
Switches  
Ringing  
Switches  
Test  
Switches  
1
State  
P3  
P2  
P1  
OFF  
x
1
Idle/Talk  
Test  
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
ON  
OFF  
OFF  
OFF  
ON  
OFF  
OFF  
ON  
OFF  
ON  
1
1
1
1
1
1
1
Ringing  
All-Off  
OFF  
OFF  
OFF  
ON  
OFF  
OFF  
OFF  
ON  
Idle/Talk  
Test/Monitor  
Ringing  
Test Ringing  
All-Off  
ON  
OFF  
OFF  
OFF  
OFF  
ON  
ON  
2
OFF  
OFF  
0
1
P1, P2, and P3 data input values are directed to a given channel when the respective LATCH logic signal is set to “0.”  
x
OFF is a per-channel control.  
x
2
3
A “0” on OFF resets the CPC75282, the device will remain in the All-Off state until OFF is returned to “1” and the next LATCH signal is  
x
applied.  
x
x
CFG is fixed at v ; if CFG switches states when V is applied, the change will be recognized by a given channel after a LATCH low  
DD  
DD  
transition is applied to that channel.  
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