CPC75282
Break-before-make operation occurs when the ringing
switches open before the break switches, SW1 and
SW2, close.
2.3.5: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B
Ringing
Return
Switch
Break
Switches
1 & 2
Ringing Test
Switch Switches
CFG=0, P3=0
P1
LATCH OFF
x
State
Timing
x
P2
4
5 & 6
x
x
x
x
x
3
x
Ringing
All-Off
1
1
0
1
1
-
Off
Off
On
On
On
Off
Off
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
current to turn off.
0
Off
0
Zero current has occurred.
SW4 has opened
All-Off
Talk
1
0
1
0
0
1
Off
On
Off
Off
Off
Off
Off
Off
Break switches close.
2.3.6 Break -Before- Make Operation
Whenever the latch enable control pin is at logic 1, the
data latch is active and data is locked. Subsequent
changes to the input controls P1, P2, and P3 will not
result in a change to the control logic or affect the
existing switch states.
Break-before-make operation can be achieved using
OFF to disable all of the switches when pulled to a
x
logic low. Although logically disabled, an active
(closed) ringing switch, SW4, will remain closed until
the next zero crossing current event.
The switches will remain in the state they were in
when the LATCH changes from logic 0 to logic 1, and
x
1. Pull OFF to a logic low to end the ringing state.
will not respond to changes in input as long as the
x
LATCH is at logic 1. However, neither the T
nor
This opens the ringing return switch, SW3, and
x
SDx
prevents any other switches from closing.
the OFF are affected by the latch function. Since
x
2. Keep OFF low for at least one-half the duration
internal thermal shutdown control and external OFF
x
x
of the ringing cycle period to allow sufficient time
for a zero crossing current event to occur and for
the circuit to enter the break-before-make state.
control is not affected by the state of the latch enable
input, T and OFF will override state control.
SDx
x
3. During the OFF low period, set the P1, P2, and
x
2.5 T Pin Description
SD
P3 inputs to the idle/talk state.
4. Release OFF , allowing the internal pull-up to
x
The T
pins are bidirectional I/O structures with
SDx
activate the break switches.
internal pull-up resistors sourced from V . As
DD
outputs, these pins indicate the status of the thermal
shutdown circuitry for the associated channels.
Typically, during normal operation, these pins will be
2.4 Data Latch
The CPC75282 has integrated transparent data
latches. The latch enable operation is controlled by
logic input levels at the LATCH pin. Data input to the
latch is via the input pins P1, P2, and P3 while the
outputs of the data latch are internal nodes used for
state control. When the latch enable control pin is at a
logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch states.
pulled up to V , but, under fault conditions that
DD
create excess thermal loading, the channels will enter
thermal shutdown and a logic low will be output.
x
As inputs, the T
pins are utilized to place the
SDx
channel into the All-Off state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than V ), Clare recommends the use
DD
of an open-collector or an open-drain type output to
control T
. This avoids sinking the T
pull up bias
SDx
SDx
current to ground during normal operation when the
All-Off state is not required. If T
is set to a logic 1 or
SDx
14
www.clare.com
R00D
CLARE [ CLARE ]
