EP9315
Enhanced Universal Platform SOC Processor
PCMCIA Write Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tADs
tA
AD setup to signal transition time
Attribute access time
0
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[(AA + 1) × tHCLK] - 14
[(HA + 1) × tHCLK] - 3
(PA + 1) × tHCLK
(AA + 1) × tHCLK
(HA + 1) × tHCLK
(PA + 1) × tHCLK
(AC + 1) × tHCLK
(HC + 1) × tHCLK
(PC + 1) × tHCLK
(AI + 1) × tHCLK
(HI + 1) × tHCLK
(PI + 1) × tHCLK
tH
Attribute hold time
tp
Attribute space pre-charge delay time
Common access time
tA
[(AC + 1) × tHCLK] - 14
[(HC + 1) × tHCLK] - 3
(PC + 1) × tHCLK
tH
Common hold time
tp
Common space pre-charge delay time
I/O access time
tA
[(AI + 1) × tHCLK] - 14
[(HI + 1) × tHCLK] - 3
(PI + 1) × tHCLK
tH
I/O hold time
tp
I/O space pre-charge delay time
MCDIR hold time
tMCDh
tDAfo
0
0
-
-
DATA invalid delay time
tADs
AD
MCEHn/
MCELn/
MCREGn
tp
tA
tH
MCWRn/
IOWRn
tMCDh
MCDIR
tDAfo
DA
(out)
MCWAITn (see Note 1)
Figure 18. PCMCIA Write Cycle Timing Measurement
Note: 1 - MCWAITn asserted will extend the MCWR / IOWR strobe time.
DS638PP4
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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