EP9315
Enhanced Universal Platform SOC Processor
ADDR valid
(Note 1)
t9
t1
t2
t2i
DIORn/
DIOWn
t0
tDDV
WRITE
DD (7:0)
(Note 2)
t3
t4
READ
DD (7:0)
(Note 2)
t5
t6
t6z
IORDY
(Note 3,3-1)
tA
IORDY
(Note 3,3-2)
tC
tRD
IORDY
(Note 3,3-3)
tB
tC
Note: 1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is
to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY
are described in the following three cases:
3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation
and may be asserted for no more than tC before release: no wait generated.
3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than tC
before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated
and DIORn is asserted, the device shall place read data on DD (7:0) for tRD before asserting IORDY.
Figure 19. Register Transfer to/from Device
DS638PP4
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