EP9315
Enhanced Universal Platform SOC Processor
12-channel DMA Controller
Table P. General Purpose Input/Output Pin Assignment
The DMA module contains 12 separate DMA channels.
Ten of these may be used for peripheral-to-memory or
memory-to-peripheral access. Two of these are
dedicated to memory-to-memory transfers. Each DMA
channel is connected to the 16-bit DMA request bus.
Pin Mnemonic
Pin Name - Description
Expanded General Purpose Input / Output
Pins with Interrupts
EGPIO[15:0]
FGPIO[7:0]
Expanded General Purpose Input / Output
Pins with Interrupts
The request bus is a collection of requests, Serial Audio,
and UARTs. Each DMA channel can be used
independently or dedicated to any request signal. For
each DMA channel, source and destination addressing
can be independently programmed to increment,
decrement, or stay at the same value. All DMA
addresses are physical, not virtual addresses.
Note: Port F defaults as PCMCIA pins. Port F must be
configured by software to be used as GPIO.
Reset and Power Management
The chip may be reset through the PRSTn pin or through
the open drain common reset pin, RSTOn.
PCMCIA Interface
Clocks are managed on a peripheral-by-peripheral basis
and may be turned off to conserve power.
The EP9315 has a single PCMCIA port which can be
used to access either 8 or 16-bit devices.
The processor clock is dynamically adjustable from 0 to
200 MHz (184 MHz for industrial conditions).
Table S. PCMCIA Interface
Table Q. Reset and Power Management Pin Assignments
Pin Mnemonic
Pin Name - Description
VS1
VS2
Voltage sense
Pin Mnemonic
Pin Name - Description
Voltage sense
PRSTn
RSTOn
Power On Reset
MCD1
Card detect
User Reset In/Out – Open Drain –
Preserves Real Time Clock value
MCD2
Card detect
MCBVD1
MCBVD2
MCDIR
Voltage detection / status change
Voltage detection
Hardware Debug Interface
Data transceiver direction control
Data bus transceiver enable
Address bus transceiver enable
Memory card register
Memory card high byte select
Memory card low byte select
I/O card read
The JTAG interface allows use of ARM’s Multi-ICE or
other in-circuit emulators.
MCDAENn
MCADENn
MCREGn
MCEHn
MCELn
Note: The JTAG interface does not support boundary scan.
Table R. Hardware Debug Interface
Pin Mnemonic
Pin Name - Description
IORDn
IOWRn
I/O card write
TCK
JTAG Clock
MCRDn
MCWRn
READY
WP
Memory card read
Memory card write
Ready / interrupt
TDI
JTAG Data In
TDO
TMS
TRSTn
JTAG Data Out
JTAG Test Mode Select
JTAG Port Reset
Write protect
MCWAITn
MCRESETn
Wait Input
Card reset
Internal Boot ROM
The Internal 16-kbyte ROM allows booting from FLASH
memory, SPI or UART. Consult the EP93xx User’s
Manual for operational details
DS638PP4
©Copyright 2005 Cirrus Logic (All Rights Reserved)
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