EP9315
Enhanced Universal Platform SOC Processor
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Timing and interface signals for digital LCD and TFT
displays
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:
Full programmability for either non-interlaced or dual-
scan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
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Support for 4-, 5-, 7-, or 8-wire analog resistive touch
screens.
Pixel depths of 4, 8, 16, or 24 bits per pixel or 256
levels of grayscale
Flexibility - unused lines may be used for temperature
sensing or other functions.
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Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
Touch screen interrupt function.
Table G. Touch Screen Interface with 12-bit Analog-to-Digital
Converter Pin Assignments
8-bit interface to low end panel
Pin Mnemonic
Pin Description
Table F. LCD Interface Pin Assignments
Xp, Xm
Touch screen ADC X Axis
Touch screen ADC Y Axis
Pin Mnemonic
Pin Description
Yp, Ym
SPCLK
Pixel Clock
Touch screen ADC X Axis
Voltage Feedback
SXp, SXm
P[17:0]
Pixel Data Bus [17:0]
Touch screen ADC Y Axis
Voltage Feedback
Horizontal
Synchronization / Line Pulse
SYp, SYm
HSYNC / LP
Vertical or Composite
Synchronization / Frame Pulse
VCSYNC / FP
64-Key Keypad Interface
BLANK
Composite Blank
The keypad circuitry scans an 8 x 8 array of 64 normally
open, single-pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16 column/row
pins may be used as general purpose I/O. The Keypad
interface:
BRIGHT
Pulse Width Modulated Brightness
Graphics Accelerator
The EP9315 contains a hardware graphics acceleration
engine that improves graphic performance by handling
block copy, block fill and hardware line draw operations.
The Graphics Accelerator is used in the system to off-
load graphics operations from the processor.
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Provides scanning, debounce, and decoding for a 64-
key switch array.
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Scans an 8-row by 8-column matrix.
May decode 2 keys at once.
Pixel depths supported by the Graphics Accelerator are
4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode
can be operated as packed (4 pixels every 3 words) or
unpacked (1 pixel per word with the high byte unused.)
Generates an interrupt when a new stable key is
determined.
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Also generates a 3-key reset interrupt.
The block copy operations of the Graphics Accelerator
are similar to a DMA (Direct Memory Access) transfer
that understands pixel organization, block width,
transparency, and transformation from 1bpp to higher 4,
8, 16 or 24bpp.
Table H. 64-Key Keypad Interface Pin Assignments
Pin
Pin Mnemonic
Alternative Usage
Description
Key Matrix Column
Inputs
The line draw operations also allow for solid lines or
dashed lines. The colors for line drawing can be either
foreground color and background color or foreground
color with the background being transparent.
COL[7:0]
ROW[7:0]
General Purpose I/O
General Purpose I/O
Key Matrix Row
Inputs
Touch Screen Interface with 12-bit Analog-
to-digital Converter (ADC)
The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
8
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DS638PP4
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