EP9315
Enhanced Universal Platform SOC Processor
Memory Interface
Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
tclk_high
tclk_low
tclkrf
Min
Typ
Max
Unit
(tHCLK) / 2
SDCLK high time
SDCLK low time
SDCLK rise/fall time
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
(tHCLK) / 2
-
2
-
-
-
-
-
-
4
8
-
td
Signal delay from SDCLK rising edge time
Signal hold from SDCLK rising edge time
DQMn delay from SDCLK rising edge time
DQMn hold from SDCLK rising edge time
DA valid setup to SDCLK rising edge time
DA valid hold from SDCLK rising edge time
-
th
1
-
tDQd
tDQh
tDAs
8
-
1
2
3
-
tDAh
-
SDRAM Load Mode Register Cycle
tclk_low
tclk_high
tclkrf
SDCLK
td
th
SDCSn
RASn
CASn
SDWEn
DQMn
AD
OP-Code
DA
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
DS638PP4
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