CS8900A
Crystal LAN™ Ethernet Controller
3.3.2 Allowing Time for Reset Operation
set (except EEPROM reset). The use of an
EEPROM is optional.
After a reset, the CS8900A goes through a self
configuration. This includes calibrating on-chip
analog circuitry, and reading EEPROM for va-
lidity and configuration. Time required for the
reset calibration is typically 10 ms. Software
drivers should not access registers internal to
the CS8900A during this time. When calibra-
tion is done, bit INITD in the Self Status Regis-
ter (register 16) is set indicating that
initialization is complete, and the SIBUSY bit in
the same register is cleared indicating the EE-
PROM is no longer being read or pro-
grammed.
The CS8900A operates with any of six stan-
dard EEPROM’s shown in Table 5.
3.3.3 Bus Reset Considerations
After reset, the CS8900A packet page pointer
register (IObase+0Ah) is set to 3000h. The
3000h value can be used as part of the
CS8900A signature when the system scans
for the CS8900A. See Section 4.10 on
page 75.
After a reset, the ISA bus outputs INTRx and
DMARQx are 3-Stated, thus avoiding any in-
terrupt or DMA channel conflicts on the ISA
bus at power-up time.
3.3.4 Initialization
After each reset (except EEPROM Reset), the
CS8900A checks the sense of the EEDataIn
pin to see if an external EEPROM is present. If
EEDI is high, an EEPROM is present and the
CS8900A automatically loads the configura-
tion data stored in the EEPROM into its inter-
nal registers (see next section). If EEDI is low,
an EEPROM is not present and the CS8900A
comes out of reset with the default configura-
tion shown in Table 4.
A low-cost serial EEPROM can be used to
store configuration information that is automat-
ically loaded into the CS8900A after each re-
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