CS8900A
Crystal LAN™ Ethernet Controller
memory. The CS8900A has three pairs of
chip-wide reset, all circuitry and registers in
DMA pins that can be connected directly to the the CS8900A are reset.
three 16-bit DMA channels of the ISA bus.
Only one DMA channel is used at a time. It is
3.3.1.2 Power-Up Reset
When power is applied, the CS8900A main-
selected during initialization by writing the
number of the desired channel (0, 1 or 2) into
PacketPage Memory base + 0024h. Unused
DMA pins are placed in a high-impedance
state. The selected DMA request pin goes
high when the CS8900A has received frames
to transfer to the host memory via DMA. If the
DMABurst bit (register 17, BusCTL, Bit B) is
clear, the pin goes low after the DMA operation
is complete. If the DMABurst bit is set, the pin
goes low 32 µs after the start of a DMA trans-
fer.
tains reset until the voltage at the supply pins
reaches approximately 2.5 V. The CS8900A
comes out of reset once Vcc is greater than
approximately 2.5 V and the crystal oscillator
has stabilized.
3.3.1.3 Power-Down Reset
If the supply voltage drops below approximate-
ly 2.5 V, there is a chip-wide reset. The
CS8900A comes out of reset once the power
supply returns to a level greater than approxi-
mately 2.5 V and the crystal oscillator has sta-
bilized.
The DMA pin pairs are arranged on the
CS8900A to facilitate board layout. Crystal
recommends the configuration in Table 3
when connecting these pins to the ISA bus.
3.3.1.4 EEPROM Reset
There is a chip-wide reset if an EEPROM
checksum error is detected (see Section 3.4
on page 21).
CS8900A DMA
Signal (Pin #)
ISA DMA
Signal
PacketPage
base + 0024h
3.3.1.5 Software Initiated Reset
DMARQ0 (Pin 15)
DMACK0 (Pin 16)
DMARQ1 (Pin 13)
DMACK1 (Pin 14)
DMARQ2 (Pin 11)
DMACK2 (Pin 12)
DRQ5
DACK5
DRQ6
0000h
0001h
0002h
There is a chip-wide reset whenever the RE-
SET bit (Register 15, SelfCTL, Bit 6) is set.
DACK6
DRQ7
3.3.1.6 Hardware (HW) Standby or Suspend
The CS8900A goes though a chip-wide reset
whenever it enters or exits either HW Standby
mode or HW Suspend mode (see Section 3.7
DACK7
Table 3. DMA Assignments
For a description of DMA mode, see on page 27 for more information about HW
Section 5.3 on page 90.
Standby and Suspend).
3.3 Reset and Initialization
3.3.1.7 Software (SW) Suspend
Whenever the CS8900A enters SW Suspend
mode, all registers and circuits are reset ex-
cept for the ISA I/O Base Address register (lo-
cated at PacketPage base + 0020h) and the
SelfCTL register (Register 15). Upon exit,
there is a chip-wide reset (see Section 3.7 on
page 27 for more information about SW Sus-
pend).
3.3.1 Reset
Seven different conditions cause the
CS8900A to reset its internal registers and cir-
cuits.
3.3.1.1 External Reset, or ISA Reset
There is a chip-wide reset whenever the RE-
SET pin is high for at least 400 ns. During a
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