CS8900A
Crystal LAN™ ISA Ethernet Controller
0120h) to assess the status of the receive frame
and sees the contents of the RxEvent register
(Register 4) with the RxOK bit (Bit 8) set.
The byte count register resides at PacketPage base
+ 50h.
Following an RxDest or Rx128 interrupt the regis-
ter contains the number of bytes which are avail-
able to be read by the CPU. When the end of frame
is reached, the count contains the final count value
for the frame, including the allowance for the Buff-
erCRC option. When this final count is read by the
CPU the count register is set to zero. Therefore to
read a complete frame using the byte count register,
the register can be read and the data moved until a
count of zero is detected. Then the RxEvent regis-
ter can be read to determine the final frame status.
3) The host reads the receive frame’s length from
the RxLength register (PacketPage base +
0402h).
4) The host reads the frame data by executing 32
consecutive MOV instructions starting with
PacketPage base + 0404h.
The memory map of the 64-byte frame is given in
Table 23.
Memory Space Description of Data Stored in On-
Word Offset
chip RAM
The sequence is as follows:
0400h
RxStatus Register (the host may
skip reading 0400h since RxEvent
was read from the ISQ.)
1) At the start of a frame, the byte counter matches
the incoming character counter. The byte
counter will have an even value prior to the end
of the frame.
0402h
RxLength Register (In this example,
the length is 40h bytes. The frame
starts at 0404h, and runs through
0443h.)
2) At the end of the frame, the final count, includ-
ing the allowance for the CRC (if the Buffer-
CRC option is enabled), is held until the byte
counter is read.
0404h to 0409h 6-byte Source Address.
040Ah to 040Fh 6-byte Destination Address.
0410h to 011h 2-byte Length or Type Field.
0412h to 043Fh 46 bytes of data.
0440h
0442h
CRC, bytes 1 and 2
CRC, bytes 3 and 4
3) When a read of the byte counter returns a count
of zero, the previous count was the final count.
The count may now have an odd value.
Table 23. Example Memory Map
4) RxEvent should be read to obtain a final status
of the frame, followed by a Skip command to
complete the operation.
5.2.9 Receive Frame Byte Counter
The receive frame byte counter describes the num-
ber of bytes received for the current frame. The
counter is incremented in real time as bytes are re- Note that all RxEvent’s should be processed before
ceived from the Ethernet. The byte counter can be
used by the driver to determine how many bytes are
using the byte counter. The byte counter should be
used following a BufEvent when RxDest or Rx128
available for reading out of the CS8900A. Maxi- interrupts are enabled.
mum Ethernet throughput can be achieved by using
5.3 Receive Frame Address Filtering
I/O or memory modes, and by dedicating the CPU
to reading this counter, and using the count to read
the frame out of the CS8900A at the same time it is
being received by the CS8900A from the Ethernet
(parallel frame-reception and frame-read-out
tasks).
The CS8900A is equipped with a Destination Ad-
dress (DA) filter used to determine which receive
frames will be accepted. (A receive frame is said to
be "accepted" by the CS8900A when the frame
data are placed in either on-chip memory, or in host
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
87
CIRRUS [ CIRRUS LOGIC ]
