CS8900A
Crystal LAN™ ISA Ethernet Controller
the receive frame by reading the BufEvent reg-
ister (Register C), either directly or through the
ISQ.
There are three possible ways that the host can
learn the status of a particular frame. It can:
1) Read the Interrupt Status Queue;
When the CS8900A commits buffer space to a par-
ticular held receive frame (termed a committed re-
ceived frame), no data from subsequent frames can
be written to that buffer space until the frame is
freed from commitment. (The committed received
frame may or may not have been received error
free.)
2) Read the RxEvent register directly (Register4);
or
3) Read the RxStatus register (PacketPage base +
0400h).
5.2.7 Receive Frame Visibility
Only one receive frame is visible to the host at a
A received frame is freed from commitment by any time. The receive frame's status can be read from
one of the following conditions:
the RxStatus register (PacketPage base + 0400h),
and its length can be read from the RxLength reg-
ister (PacketPage base + 0402h). For more infor-
mation about Memory space operation, see
Section 4.9 on page 74. For more information
about I/O space operation, see Section 4.10 on
page 76.
1) The host reads the entire frame sequentially in
the order that it was received (first byte in, first
byte out).
Or:
2) The host reads part or none of the frame, and
then issues a Skip command by setting the
Skip_1 bit (Register 3, RxCFG, bit 6).
5.2.8 Example of Memory Mode Receive Opera-
tion
Or:
A common length for short frames is 64 bytes, in-
cluding the 4-byte CRC. Suppose that such a frame
has been received with the CS8900A configured as
follows:
3) The host reads part of the frame and then reads
the RxEvent register (Register 5), either direct-
ly or through the ISQ, and learns of another re-
ceive frame. This condition is called an
"implied Skip". Ensure that the host does not do
“implied skips.”
•
The BufferCRC bit (Register 3, RxCFG, Bit B)
is set causing the 4-byte CRC to be buffered
with the rest of the receive data.
Both early interrupts are disabled whenever there is
a committed receive frame waiting to be processed
by the host.
•
The RxOKA bit (Register 5, RxCTL, Bit 8) is
set, causing the CS8900A to accept good
frames (a good frame is one with legal length
and valid CRC).
5.2.6 Transferring Held Receive Frames
•
The RxOKiE bit (Register 3, RxCFG, Bit 8) is
set, causing an interrupt to be generated when-
ever a good frame is received.
The host can read-out held receive frames in Mem-
ory or I/O space. To transfer frames in Memory
space, the host executes repetitive Move instruc-
tions (REP MOVS) from PacketPage base +
0404h. To transfer frames in I/O space, the host ex-
ecutes repetitive In instructions (REP IN) from I/O
base + 0000h, with status and length preceding the
frame.
Then the transfer to the host would proceed as fol-
lows:
1) The CS8900A generates an RxOK interrupt to
the host to signal the arrival of a good frame.
2) The host reads the ISQ (PacketPage base +
CIRRUS LOGIC PRODUCT DATA SHEET
86
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
