CS8900A
Crystal LAN™ ISA Ethernet Controller
5.2.2.3 Selecting which Events Cause Interrupts
Register 13, LineCTL
Bit Name Operation
SerRxON When set, reception enabled.
Bit
6
The RxCFG register (Register 3) and the BufCFG
register (Register B) are used to determine which
receive events will cause interrupts to the host pro-
cessor. Table 21 describes the interrupt enable (iE)
bits in these registers.
8
AUIonly
When set, AUI selected (takes
precedence over AutoAUI/10BT).
9
AutoAUI/10BT When set, automatic interface
selection enabled. When both bits
8 and 9 are clear, 10BASE-T
selected.
Register 3, RxCFG
Bit Bit Name
Operation
E
LoRx Squelch When set, receiver squelch level
reduced by approximately 6 dB.
8
RxOKiE When set, there is an interrupt if a
frame is received with valid length
and CRC*.
Table 18. Physical Interface Configuration
C CRCerroriE When set, there is an interrupt if a
frame is received with bad CRC*.
memory via DMA). Table 19 describes the config-
uration bits in this register. Refer to Section 5.3 on
page 87 for a detailed description of Destination
Address filtering.
D
RuntiE
When set, there is an interrupt if a
frame is received that is shorter than
64 bytes*.
E ExtradataiE When set, there is an interrupt if a
frame is received that is longer than
1518 bytes*.
Register 5, LRxCTL
Bit Bit Name
Operation
6
IAHashA When set, Individual Address frames
that pass the hash filter are
accepted*.
* Must also pass the DA filter before there is an interrupt.
Table 20.
7
8
Promis When set, all frames are accepted*.
cuousA
Register B, BufCFG
Bit
Bit Name
Operation
RxOKA When set, frames with valid length
and CRC and that pass the DA filter
are accepted.
7
RxDMAiE When set, there is an interrupt if
one or more frames are trans-
ferred via DMA.
9
MulticastA When set, Multicast frames that pass
the hash filter are accepted*.
A
B
RxMissiE When set, there is an interrupt if a
frame is missed due to insufficient
receive buffer space.
A
IndividualA When set, frames with DA that
matches the IA at PacketPage base
+ 0158h are accepted*.
Rx128iE When set, there is an interrupt
after the first 128 bytes of receive
data have been buffered.
B
Broad- When set, all broadcast frames are
castA
accepted*.
D
F
MissOvfloiE When set, there is an interrupt if
the RxMISS counter overflows.
C CRCerrorA When set, frames with bad CRC that
pass the DA filter are accepted.
RxDestiE When set, there is an interrupt
after the DA of an incoming frame
has been buffered.
D
RuntA
When set, frames shorter than 64
bytes that pass the DA filter are
accepted.
Table 21. Registers 3 and B Interrupt Configuration
E ExtradataA When set, frames longer than 1518
bytes that pass the DA filter are
accepted (only the first 1518 bytes
are buffered).
5.2.2.4 Choosing How to Transfer Frames
The RxCFG register (Register 3) and the BusCTL
register (Register 17) are used to determine how
frames will be transferred to host memory, as de-
scribed in Table 22.
* Must also meet the criteria programmed into bits 8, C, D,
and E.
Table 19. Frame Acceptance Criteria
CIRRUS LOGIC PRODUCT DATA SHEET
82
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
