CS8900A
Crystal LAN™ ISA Ethernet Controller
host memory. Preceding the frame data are the
contents of the RxStatus register (PacketPage
base + 0400h) and the RxLength register (Pack-
etPage base + 0402h).
contents of the target register is then mapped into
the PacketPage Data Port (I/O base + 000Ch).
If the host needs to access a sequential block of reg-
isters, the MSB of the PacketPage address of the
first word to be accessed should be set to "1". The
PacketPage Pointer will then move to the next word
location automatically, eliminating the need to set-
up the PacketPage Pointer between successive ac-
cesses (see Figure 18).
For a more detailed description of receive, see
Section 5.2 on page 79.
4.10.10 Accessing Internal Registers
To access any of the CS8900A’s internal registers
in I/O Mode, the host must first setup the Pack-
etPage Pointer. It does this by writing the Pack-
etPage address of the target register to the
PacketPage Pointer Port (I/O base + 000Ah). The
4.10.11 Polling the CS8900A in I/O Mode
If interrupts are not used, the host can poll the
CS8900A to check if receive frames are present
and if memory space is available for transmit.
CIRRUS LOGIC PRODUCT DATA SHEET
78
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
